{"title":"System level power modeling and simulation of high-end industrial network-on-chip","authors":"A. Bona, V. Zaccaria, R. Zafalon","doi":"10.1007/1-4020-8076-X_13","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"80","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1007/1-4020-8076-X_13","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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