The feasibility study of designing a FPGA multiplier-core on finite field

Abstract

In digital system development, the CPLD/FPGA is usually used to implement basic function blocks for the purposes of testing, integration and IP proof. The advantages of CPLD/FPGA are high efficiency, flexibility and easy reconfiguration. Taking AES as an example, this application needs more flexible transformations to design for diversity. In order to meet such requirements without declining the performance, a modified architecture of FPGA is proposed to increase the overall efficiency and keep high throughput. A finite field multiplier is provided for the explanation of the newly developed core. The parallel and pipelined design in FPGA can replace high-speed VLSI chip with dynamic reconfigurability.