X. S. Wang, Xin Wang, Z. Dong, Fei Lu, Li Wang, R. Ma, Chen Zhang, Albert Z. H. Wang, C. Yue, Dawn Wang, A. Joseph
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引用次数: 0
Abstract
SPMT-ESD interaction and co-design analysis are critical to designing SPMT with high ESD protection. New co-design approach helps to deliver a high linearity SP10T with 8500V ESD protection in SOI CMOS, compared favorable to the state-of-the-art with 0-700V ESD protections [1-3].
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