Development of Resynthesis Flow for Improving Logical Masking Features of Combinational Circuits

Abstract

This paper is devoted to development of combinational circuits resynthesis flow aimed at soft error tolerance improvement. Sensitivity factor, i.e. average number of non-reliable elements, is used as fault-tolerance metric, as well as circuit's “sensitive area” which additionally considers areas of standard cells. Re-synthesis algorithm involves iterative replacement of some sections of circuit by functionally equivalent blocks with better masking properties. Result can be achieved by adding redundancy, or by implementing more optimal structure with respect to fault tolerance. When estimating masking properties, circuit section is considered to be separate circuit, which speeds up program performance. We use input test patterns for subcircuit in accordance with their probabilities and observability of subcircuit outputs at primary circuit outputs to take into account influence of surrounding gates during optimal structure selection. The algorithm was tested on circuits from ISCAS'85 and LGSynth'89 benchmarks synthesized with different optimization parameters using two different standard digital libraries.