An Efficient ALU Architecture Topology for Nanotechnology Applications

Abstract

In this paper, a highly efficient ALU architecture is designed using Carbon Nanotube Field effect Transistor(CNTFET) and conventional MOSFET. High performing Multiplexer (Mux) based full adder is used for this purpose. First the performance of Transmission gate(TG) based Multiplexer and Pass transistor logic(PTL) based multiplexer are compared. Extensive performance analysis of several low transistor count hybrid adders has been done based on their power, delay, and PDP and thereby establishing Mux based Full Adder(FA) as the more efficient adder topology. The 4 bit ALU is implemented using the Mux based adder and its performance is compared with its CNTFET implementation. All the simulations are done using Cadence Virtuoso by 45nm technology for MOSFET and 10nm technology for CNTFET at 27°C for a supply voltage range of 0.6V to 1.2V. The CNTFET based circuits were designed to appraise their compatibility with conventional transistors and show considerable performance improvement.