A 59ns 256K DRAM using LD3technology and double level metal

Abstract

A 256K NMOS PRAM with a typical read access time of 5911s after RAS at 80 C and at 4.5V, (Figure 1 ) will be described. Page mode read and write cycles at tester-limited cycle rates of 55ns have been achieved; Figure 2. One key element in achieving this performance was a triplediffused LD3 NMOS transistor structure, a combination of a double-diffused lightly-doped phosphorus junction, surrounded by a halo of boron, and a deep arsenic-diffused heavily-doped junction as the sonrce/drain junction. The structure is similar to the double implanted structure reported earlier', with the following characteristics: N+ junction can be independently driven deep to reduce the parasitic resistance; the Njunction length, depth, and doping concentration can be adjusted according to their needs; the gate to source/drain overlap capacitance is small; boron halo, together with a channel implant control the Vt and provide compensation of the short channel Vt falloff, and the lightly-doped drain provides significantly reduced impact ionization. A second element of the circuit is the use of a two-level metal interconnect system. The additional level of low-resistance interconnect allows both the bit lines and word lines to have minimal transient delays. Double level metal also provides a good power bussing network in the periphery.