A 0.696-mW 9-bit 80-MS/s 2-b/cycle Nonbinary SAR ADC in 130-nm SOI CMOS

Abstract

A 2b/cycle nonbinary successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this brief. Two capacitor DACs, a Signal-DAC (SIG-DAC) and a Reference-DAC (REF-DAC), which are used to implement the 2b/cycle architecture, are designed to be nonbinary weighted. Such an approach can make the ADC robust enough to comparator offset variations and mismatch between DACs. In DAC settling phase, with splitting capacitors array, both the SIGDAC and REF-DAC capacitors use monotonic switching method, which can reduce the power dissipation and speed up the conversion. A prototype 9b ADC using 130-nm Silicon-On-Insulator (SOI) CMOS process works at 80MS/s from 1.2V supply, the simulation results shows a signal-to-noise plus distortion ratio (SNDR) of 50.40dB and a spurious-free dynamic range (SFDR) of 52.94dB. The total power consumption of the ADC is 0.696mW and the FoM is 32 fJ/conversion-step.