Impact of Variation in Barrier Thickness on a Gate-Engineered TM-DG Heterostructure MOSFET to Suppress SCE's and it's Analog, RF, Linearity Performance Investigation for SOC Applications

Abstract

In this work, a thorough inspection of DC, Analog, RF, Linearity and SCE's parameter analysis of Gate-Engineered TM-DG heterostructure MOSFET is carried out taking in to account the effect of changing the thickness of the barrier layer. The performance of the proposed device is investigated by evaluating some standard figure of merits (FOMs) like transconductance (gm), Output resistance (ROUT), Intrinsic Gain (gmRout), Transconductance Generation factor (gm/ID), gate capacitance, cutoff frequency(fT), maximum frequency of oscillation (fmax), Gain Bandwidth Product (GBW), VIP2, VIP3and 1 dB compression. All these FOMs are analyzed by varying the thickness of the barrier from 1 nm to 4 nm using TCAD simulation. The simulation results clarifies that performance of TM-DG heterostructure Metal field effect transistor (1:2:3) is affected as thickness of the barrier is scaled down.