Low-cost video transform for HEVC

Abstract

In this paper, we present a hardware design which can support the inverse transform size from 32×32 in high efficiency video coding (HEVC) and is implemented by a using single 1-D IDCT core with a memory to low cost architecture. The proposed 1-D IDCT core employs two calculating paths to achieve a high throughput rate and is implemented by a 1-D inverse transform which can calculate 1st-D and 2nd-Ddata simultaneously in two parallel paths. The proposed 2-D transform core can implement a throughput rate of 332-Mpels/s with 129k gate area.