A Three-Layer Resist Process for T - and T -Gates in High Electron Mobility Transistor Fabrication

Abstract

By utilizing a novel three-layer resist process, InAIN/AIN/GaN T - and T -gate high electron mobility transistors with 0.1 μm gate lengths and below have been demonstrated. This process is based on direct electron-beam lithography with a single exposure step. Furthermore, the effect of different T -gate shapes on RF power performance is reported. A T -gate shift to the source side of the Ohmic contact, results in lower gate-to-drain capacitance and in higher transistor RF transducer gain Gt.