TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for cell-internal defects

Abstract

Some cell-internal defects can be modeled as small delay faults. This paper presents a timing-aware gate exhaustive transition fault (TARGET) ATPG for cell-internal defects. Our ATPG tries to launch gate output transitions from as many different gate input transitions as possible. We defined TARGET coverage and TARGET SDQL to evaluate the quality of our test sets. TARGET does not require exhaustive SPICE simulation to characterize each library cell. Compared with traditional N-detect and timing-aware test patterns, the proposed TARGET test patterns have better TARGET coverage given the same test length.