Challenges in the design of frequency synthesizers for wireless applications

Behzad Razavi
{"title":"Challenges in the design of frequency synthesizers for wireless applications","authors":"Behzad Razavi","doi":"10.1109/CICC.1997.606653","DOIUrl":null,"url":null,"abstract":"This paper describes the challenges in the design of frequency synthesizers used in wireless transceivers. Following a review of design issues and the effect of nonidealities, we present a number of synthesizer architectures along with their merits and drawbacks. We also describe the difficulties in the design of some of the building blocks and consider the role of synthesizers in emerging applications.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"82 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"123","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1997.606653","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 123

Abstract

This paper describes the challenges in the design of frequency synthesizers used in wireless transceivers. Following a review of design issues and the effect of nonidealities, we present a number of synthesizer architectures along with their merits and drawbacks. We also describe the difficulties in the design of some of the building blocks and consider the role of synthesizers in emerging applications.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
无线应用频率合成器设计中的挑战
本文介绍了无线收发器频率合成器设计中的难点。在回顾了设计问题和非理想性的影响之后,我们提出了一些合成器架构以及它们的优点和缺点。我们还描述了一些构建模块设计中的困难,并考虑了合成器在新兴应用中的作用。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
DFT for embedded charge-pump PLL systems incorporating IEEE 1149.1 Self-calibration of digital phase-locked loops Multi-layer over-the-cell routing with obstacles A 2.4 V, 700 /spl mu/W, 0.18 mm/sup 2/ second-order demodulator for high-resolution /spl Sigma//spl Delta/ DACs A single-chip controller for 1.2 Gbps shared buffer ATM switches
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1