{"title":"A new fabrication method of short channel MOS FET-multiple walls self-aligned MOS FET","authors":"H. Shibata, H. Iwasaki, T. Oku, Y. Tarui","doi":"10.1109/IEDM.1977.189269","DOIUrl":null,"url":null,"abstract":"The fabrication procedure and device characteristics of the new structure of the MOS FET, Multiple Walls Self-Aligned MOS FET (MSA MOS), are described. These techniques provided a novel production method for the advanced self-aligned MOST, which are especially suitable for super short channel MOS FET. Two closely spaced photoresist walls, which are photolithographically formed on a silicon wafer, protect the narrow region between the walls against the obliquely incident ion beams. By applying this shadowing effect to ion beam etching and the ion implantation process, the positions of the source, drain, gate and their electrodes can at last be delineated by only a single photomask or one step electron beam exposure. This process will reduce the dimensions of MOS FET, resulting in further integration in MOS LSI. By using the MSA process procedure, poly silicon gate MOS FETs with a gate length of 1µm to 3µm are fabricated and tested. These transistors show good performance.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"376 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1977 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1977.189269","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
The fabrication procedure and device characteristics of the new structure of the MOS FET, Multiple Walls Self-Aligned MOS FET (MSA MOS), are described. These techniques provided a novel production method for the advanced self-aligned MOST, which are especially suitable for super short channel MOS FET. Two closely spaced photoresist walls, which are photolithographically formed on a silicon wafer, protect the narrow region between the walls against the obliquely incident ion beams. By applying this shadowing effect to ion beam etching and the ion implantation process, the positions of the source, drain, gate and their electrodes can at last be delineated by only a single photomask or one step electron beam exposure. This process will reduce the dimensions of MOS FET, resulting in further integration in MOS LSI. By using the MSA process procedure, poly silicon gate MOS FETs with a gate length of 1µm to 3µm are fabricated and tested. These transistors show good performance.