Generating synchronous timed descriptions of digital receivers from dynamic data flow system level configuration

Abstract

The system and architecture design of digital receivers for high to medium throughput communication links and similar signal processing hardware has special characteristics. The algorithm development on the system level is performed using a data flow driven simulation tool. To shorten the turn-around time in the joint optimization of algorithm and architecture we developed the concept of a tool and library support for a smooth direct transition from the untimed system level dynamic data flow specification and simulation to a synchronous timed ASIC implementation using a hardware description language. Multiple and dynamic data rates can be converted. To reuse design knowledge a library of several generic implementations is provided, which should allow to cover various trade-offs for the particular functions. The timing interface of the library allows for introduction of timing and implementation-dependent information in terms of data rates, iteration intervals (i.e. the number of clock cycles between two data items), port related latencies and control conditions (for models with dynamic rates). The system incorporates algorithms for checking whether the system is consistent and deadlock-free as well as the computation of the arrival times for the data items on the edges. The main task in the implementation of the dynamic data flow is the automatic creation of the gated clock or control signal system to enable the correct setting of algorithmic states in the system. Furthermore algorithms for detecting the registers representing the algorithmic states (which are different from pipeline registers when dealing with dynamic subgraphs) and deciding on the feasibility of the implementation have been developed.<>