Low power dissipation in BIST schemes for modified Booth multipliers

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI:10.1109/DFTVS.1999.802877

X. Kavousianos, D. Bakalis, H. T. Vergos, D. Nikolos, G. Alexiou

引用次数: 10

Abstract

Aiming at low power dissipation during testing, in this paper we present a methodology for deriving a novel BIST scheme for modified Booth multipliers. Reduction of the power dissipation is achieved by: (a) introducing a suitable test pattern generator (TPG) built of a 4-bit binary and a 4-bit Gray counter, (b) properly assigning the TPG outputs to the multiplier inputs and (c) significantly reducing the test set length. The achieved reduction of the total power dissipation is from 44.1% to 54.9%, the average reduction per test vector is from 21.4% to 36.5% while the reduction of the peaks is from 15.8% to 34.3%, depending on the implementation of the basic cells and the size of the MBM. The test application time is also reduced by 28.9% while the introduced BIST scheme implementation overhead is very small.

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改进的Booth乘法器的BIST方案的低功耗

针对测试过程中的低功耗，本文提出了一种推导改进布斯乘法器的新型BIST方案的方法。降低功耗是通过以下方式实现的:(a)引入一个由4位二进制和4位灰色计数器组成的合适的测试模式发生器(TPG)， (b)适当地将TPG输出分配给乘法器输入，以及(c)显着减少测试集长度。根据基本单元的实现和MBM的大小，实现的总功耗降低从44.1%到54.9%，每个测试向量的平均功耗降低从21.4%到36.5%，峰值功耗降低从15.8%到34.3%。测试申请时间也减少了28.9%，同时引入的BIST方案实现开销很小。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)

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