CMOS implementation of envelope detector circuit in 0.18µm Process

Abstract

This paper presents an envelope detector circuit design for RFID applications implemented in 0.18µm CMOS technology. Towards the design compatibility with standard digital CMOS process, the doubler cell, diode connected PMOS and low transconductance transistor are chosen to place in the rectifier section and to replace the conventional diode as well as the resistor. The proposed envelope detector circuit was simulated with a 150mV – 250mV input signal. With 0.2 modulation index at 900MHz carrier frequency, the power dissipation is found to be 18.8µW at 27°C.