Empirical Model of Surface Potential and Simulation Analyses for ZnO TFTs

Anirudh Aggarwal, R. Goswami, Kavindra Kandpal
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Abstract

This paper presents a study on the performance of a bottom gate ZnO thin film transistor (TFT) model through 2-D TCAD device simulations and proposes a surface potential analytical model for the same. The simulation has been calibrated with a fabricated ZnO TFT. The analytical model is found to be in good agreement with the simulated measurements. Through further analyses on TCAD tool, the electrical characteristics of ZnO TFT have been investigated to comprehensively deduce the effect of ZnO active layer thickness, the dielectric material and the drain voltage. To obtain a significant ratio of on and off currents, and a positive gate voltage switching, gate workfunction engineering has been demonstrated.
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ZnO tft表面电位的经验模型及模拟分析
本文通过二维TCAD器件仿真研究了底栅ZnO薄膜晶体管(TFT)模型的性能,并提出了其表面电位分析模型。用制备的ZnO TFT对模拟进行了校准。分析模型与模拟测量结果吻合较好。通过对TCAD工具的进一步分析,研究了ZnO TFT的电学特性,综合推断了ZnO有源层厚度、介质材料和漏极电压对ZnO TFT的影响。为了获得显着的通断电流比和正栅极电压开关,已经演示了栅极工作函数工程。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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