A VLSI data compression chip for high-speed image compression

Abstract

A VLSI chip has been designed to perform a high-speed pyramid data compression algorithm for image processing. The algorithm implemented in the VLSI chip requires dramatically less computations yet it is an effective technique to perform the data compression. The computational complexity of the algorithm is at least 10 times less than that of the standard algorithm, JPEG while offering comparable performances in image quality to JPEG. Moreover, due to the simplified computational algorithm, the hardware complexity will be 3 to 4 times less than the VLSI chips based on JPEG, thus the cost/performance of the proposed VLSI data compression chip will be 30 to 40 times cheaper than any existing standard data compression chip.