Analysis of very large resistive networks using low distortion embedding

S. Koranne
{"title":"Analysis of very large resistive networks using low distortion embedding","authors":"S. Koranne","doi":"10.1109/ISQED.2013.6523659","DOIUrl":null,"url":null,"abstract":"VLSI designs contain very large resistive networks consisting of hundreds of millions (10e11) of resistors. Accurate parasitic extraction and analysis of such large networks is essential in many phases of the VLSI design flow. Existing techniques to analyze large resistive networks using linear solvers, despite recent optimizations, still take prohibitive computation time. In this paper a new technique based on low-distortion embedding to estimate point-to-point effective resistance is presented. Our proposed method employs recently discovered techniques from theoretical computer science to compute an ε-approximate resistance embedding matrix from which effective resistances of all node pairs can be estimated as easily as taking the Euclidean norm of column differences. The proposed method runs in almost linear time (linear in the number of resistors), and the accuracy (ε) is user specified. The method has been implemented and experimental results on large networks containing upto 10e11 nodes are presented. Compared to existing method using sparse linear solvers, our methods are more than 10 times faster on mesh networks and more importantly given a network of n nodes, allow computation of effective resistance between arbitrary node pairs in O(lg(n)) time (lg denotes logarithm to base 2).","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Symposium on Quality Electronic Design (ISQED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2013.6523659","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

VLSI designs contain very large resistive networks consisting of hundreds of millions (10e11) of resistors. Accurate parasitic extraction and analysis of such large networks is essential in many phases of the VLSI design flow. Existing techniques to analyze large resistive networks using linear solvers, despite recent optimizations, still take prohibitive computation time. In this paper a new technique based on low-distortion embedding to estimate point-to-point effective resistance is presented. Our proposed method employs recently discovered techniques from theoretical computer science to compute an ε-approximate resistance embedding matrix from which effective resistances of all node pairs can be estimated as easily as taking the Euclidean norm of column differences. The proposed method runs in almost linear time (linear in the number of resistors), and the accuracy (ε) is user specified. The method has been implemented and experimental results on large networks containing upto 10e11 nodes are presented. Compared to existing method using sparse linear solvers, our methods are more than 10 times faster on mesh networks and more importantly given a network of n nodes, allow computation of effective resistance between arbitrary node pairs in O(lg(n)) time (lg denotes logarithm to base 2).
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
基于低失真嵌入的超大电阻网络分析
VLSI设计包含由数亿(10e11)个电阻组成的非常大的电阻网络。在超大规模集成电路设计流程的许多阶段,精确的寄生提取和分析是必不可少的。使用线性求解器分析大型电阻网络的现有技术,尽管最近进行了优化,但仍然需要大量的计算时间。提出了一种基于低失真嵌入的点对点有效电阻估计方法。我们提出的方法采用了最近发现的理论计算机科学技术来计算ε-近似电阻嵌入矩阵,从该矩阵中可以很容易地估计所有节点对的有效电阻,就像取列差的欧几里得范数一样。该方法的运行时间几乎为线性(电阻器数量为线性),且精度(ε)由用户指定。该方法已在包含多达10e11个节点的大型网络上实现,并给出了实验结果。与使用稀疏线性解算器的现有方法相比,我们的方法在网状网络上的速度要快10倍以上,更重要的是,给定n个节点的网络,允许在O(lg(n))时间内计算任意节点对之间的有效阻力(lg表示以2为底的对数)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Fast FPGA-based fault injection tool for embedded processors Effective thermal control techniques for liquid-cooled 3D multi-core processors Analysis and reliability test to improve the data retention performance of EPROM circuits Increasing the security level of analog IPs by using a dedicated vulnerability analysis methodology Easy-to-build Arbiter Physical Unclonable Function with enhanced challenge/response set
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1