Design-Time Analysis of Real-Time Traffic for Networks-on-Chip using Constraint Models

Abstract

Real-time networks-on-chips (RT-NoCs) were proposed to suit the needs of communication-intensive systems with real-time requirements. However, most of the current implementations found in the literature are based on custom routers, thus requiring a complete redesign of the interconnect architecture. This work presents a novel approach to tackle the analysis and scheduling of real-time traffic that requires no special mechanism to be implemented within the NoC design. Our solution relies on an auxiliary hardware module to synchronize the injection of packets into the network instead of custom routers, benefiting existing non-RT NoC designs. Our approach guarantees scheduled traffic to be congestion-free by using a design-time optimization process. Results present a didactic proof-of-concept using a synthetic application mapped onto a small NoC design.