Pub Date : 2022-08-22DOI: 10.1109/SBCCI55532.2022.9893244
R. Faccenda, Gustavo Comarú, L. L. Caimi, F. Moraes
Many-core systems-on-chip (MCSoCs) contain pro-cessing elements (PEs), peripherals attached to the system, and an NoC connecting them. These systems have different flows traversing the NoC: PE-PE and PE-peripheral flows. Malicious hardware or software can hinder system security due to the resource sharing feature, such as CPU sharing for multitasking or sharing NoC links for flows belonging to different applications. Methods that isolate applications with security constraints, such as Secure Zones (SZs), protect PE-PE flows against most of the attacks reported in the literature. Proposals with methods to secure the communication with peripherals in the literature are scarce, with most of them focusing on shared memory protection. This paper presents an original approach, Secure Mapping with Access Point - SeMAP, which creates mapping policies for SZs, and communication strategies with IO devices, to protect PE-peripheral flows. Results show that the application execution time is not penalized by applying SeMAP, presenting advantages compared to a state-of-the-art approach. In terms of security, SeMAP successfully resisted an attack campaign, blocking malicious packets attempting to enter the SZ.
{"title":"Secure Communication with Peripherals in NoC-based Many-cores","authors":"R. Faccenda, Gustavo Comarú, L. L. Caimi, F. Moraes","doi":"10.1109/SBCCI55532.2022.9893244","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893244","url":null,"abstract":"Many-core systems-on-chip (MCSoCs) contain pro-cessing elements (PEs), peripherals attached to the system, and an NoC connecting them. These systems have different flows traversing the NoC: PE-PE and PE-peripheral flows. Malicious hardware or software can hinder system security due to the resource sharing feature, such as CPU sharing for multitasking or sharing NoC links for flows belonging to different applications. Methods that isolate applications with security constraints, such as Secure Zones (SZs), protect PE-PE flows against most of the attacks reported in the literature. Proposals with methods to secure the communication with peripherals in the literature are scarce, with most of them focusing on shared memory protection. This paper presents an original approach, Secure Mapping with Access Point - SeMAP, which creates mapping policies for SZs, and communication strategies with IO devices, to protect PE-peripheral flows. Results show that the application execution time is not penalized by applying SeMAP, presenting advantages compared to a state-of-the-art approach. In terms of security, SeMAP successfully resisted an attack campaign, blocking malicious packets attempting to enter the SZ.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123113837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-22DOI: 10.1109/SBCCI55532.2022.9893218
C. Gewehr, Carlis Raupp, J. Leao
Bitcoin is the most well-adopted cryptocurrency today. As of 2022, it is estimated that around US$ 4 billion are transacted daily within the Bitcoin network. Optimizing the energy expenditure of Bitcoin mining is of interest to several parties, such as end-users, who make transactions on the Bitcoin network with lower fees, miners themselves, who increase mining profits due to lower operational costs, and government regulation bodies, who minimize the environmental and power-grid impacts of mining. In this work we present a Bitcoin mining core employing several optimizations and design techniques that aim to maximize energy efficiency. Results in a 6 nm technology node show a 33% improvement in energy efficiency when compared to the state-of-the-art implementation.
{"title":"eSi-BTC: an energy efficient Bitcoin mining core","authors":"C. Gewehr, Carlis Raupp, J. Leao","doi":"10.1109/SBCCI55532.2022.9893218","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893218","url":null,"abstract":"Bitcoin is the most well-adopted cryptocurrency today. As of 2022, it is estimated that around US$ 4 billion are transacted daily within the Bitcoin network. Optimizing the energy expenditure of Bitcoin mining is of interest to several parties, such as end-users, who make transactions on the Bitcoin network with lower fees, miners themselves, who increase mining profits due to lower operational costs, and government regulation bodies, who minimize the environmental and power-grid impacts of mining. In this work we present a Bitcoin mining core employing several optimizations and design techniques that aim to maximize energy efficiency. Results in a 6 nm technology node show a 33% improvement in energy efficiency when compared to the state-of-the-art implementation.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123336337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-22DOI: 10.1109/SBCCI55532.2022.9893263
Matheus Isquierdo, Renira Soares, F. Sampaio, B. Zatt, D. Palomino
This paper presents an error resilience evaluation of the intra prediction in VVC decoders when approximate storage is employed in the Reference Line Buffer (RLB). We present an error injection framework to simulate the use of approximate storage in the RLB buffer with commonly used Bit Error Rate (BER) values from literature for SRAM and DRAM technologies. We also perform the resilience evaluation considering different decoding configurations. Our analysis characterizes how the impacts of approximation are dependent on video content and configurations. The results show that approximate storage can be used in some of the evaluated scenarios with very low degradation on the final visual quality of the decoded video sequences.
{"title":"Error Resilience Evaluation of Approximate Storage in the Intra Prediction of VVC Decoders","authors":"Matheus Isquierdo, Renira Soares, F. Sampaio, B. Zatt, D. Palomino","doi":"10.1109/SBCCI55532.2022.9893263","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893263","url":null,"abstract":"This paper presents an error resilience evaluation of the intra prediction in VVC decoders when approximate storage is employed in the Reference Line Buffer (RLB). We present an error injection framework to simulate the use of approximate storage in the RLB buffer with commonly used Bit Error Rate (BER) values from literature for SRAM and DRAM technologies. We also perform the resilience evaluation considering different decoding configurations. Our analysis characterizes how the impacts of approximation are dependent on video content and configurations. The results show that approximate storage can be used in some of the evaluated scenarios with very low degradation on the final visual quality of the decoded video sequences.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116858630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-22DOI: 10.1109/SBCCI55532.2022.9893231
Frederik Kautz, Holger Blume, C. Sauer
The complexity of modern embedded systems, especially in the areas of health, Internet of Things (IoT), or Cyber Physical Systems is continuously increasing. Due to simultaneously decreasing time to market, methods and techniques for a disciplined early Design Space Exploration (DSE) become mandatory. Recently, the Portable Test and Stimulus Standard (PSS) was introduced as a more abstract level to describe test intend, helping with software driven verification of complex systems. Our work aims at its use early in the design cycle, which still suffers from non-optimal representation of applications namely regarding expressiveness, early availability, reuse and path to implementation. Following an analysis of recent work, we propose an early DSE methodology based on PSS following the Y-chart to tackle before mentioned aspects. From a UML like description of a high-end hearing aid algorithm, we show the first needed steps to create valid application-to-architecture mappings, which can be used for further trade-off analysis and reused within and between common development cycles.
{"title":"Methodology for an Early Exploration of Embedded Systems using Portable Test and Stimulus Standard","authors":"Frederik Kautz, Holger Blume, C. Sauer","doi":"10.1109/SBCCI55532.2022.9893231","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893231","url":null,"abstract":"The complexity of modern embedded systems, especially in the areas of health, Internet of Things (IoT), or Cyber Physical Systems is continuously increasing. Due to simultaneously decreasing time to market, methods and techniques for a disciplined early Design Space Exploration (DSE) become mandatory. Recently, the Portable Test and Stimulus Standard (PSS) was introduced as a more abstract level to describe test intend, helping with software driven verification of complex systems. Our work aims at its use early in the design cycle, which still suffers from non-optimal representation of applications namely regarding expressiveness, early availability, reuse and path to implementation. Following an analysis of recent work, we propose an early DSE methodology based on PSS following the Y-chart to tackle before mentioned aspects. From a UML like description of a high-end hearing aid algorithm, we show the first needed steps to create valid application-to-architecture mappings, which can be used for further trade-off analysis and reused within and between common development cycles.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127580950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-22DOI: 10.1109/SBCCI55532.2022.9893233
Suoyue Zhan, Chunhong Chen
Aging effect is one of the critical factors causing circuit reliability degradation due to negative bias temperature instability (NBTI) with continuous and intense logic operation. While there is no lack of research work on aging-related reliability analysis at transistor- or gate-level, little has been done to estimate the reliability at circuit-level. This makes it difficult for the designers to predict the circuit lifetime. To fill this gap, this paper proposes a reliability estimation model to target the reliability degradation at the output of integrated circuits. Simulations on benchmark circuits show that the reliability degradation rate ranges from 1.5% to 8.2% over one-year period, depending on specific circuits.
{"title":"Circuit Reliability Analysis with Considerations of Aging Effect","authors":"Suoyue Zhan, Chunhong Chen","doi":"10.1109/SBCCI55532.2022.9893233","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893233","url":null,"abstract":"Aging effect is one of the critical factors causing circuit reliability degradation due to negative bias temperature instability (NBTI) with continuous and intense logic operation. While there is no lack of research work on aging-related reliability analysis at transistor- or gate-level, little has been done to estimate the reliability at circuit-level. This makes it difficult for the designers to predict the circuit lifetime. To fill this gap, this paper proposes a reliability estimation model to target the reliability degradation at the output of integrated circuits. Simulations on benchmark circuits show that the reliability degradation rate ranges from 1.5% to 8.2% over one-year period, depending on specific circuits.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127636622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-22DOI: 10.1109/SBCCI55532.2022.9893239
Matheus Cortez, A. Girardi, P. Aguirre
Currently, mobile and wearable devices have digital audio signal processing capabilities. Since the nature of audio signals is analog, there is a need to use analog-to-digital converters (ADCs) with high-resolution for a high signal-to-noise ratio audio acquisition. This paper presents the high-level design of a continuous-time third-order sigma-delta modulator with a FIR DAC for audio devices, using a supply voltage of 0.5 V. The design is carried out using the Delta-sigma toolbox and a discrete-time to continuous-time (DT-CT) transformation. It was estimated that the first-integrator amplifier needs a gain of 50 dB, a GBW of 5 MHz and a slew-rate of at least $3 mathrm{V}/mu mathrm{s}$. By implementing this amplifier in VerilogA and performing a transient simulation with noise, the modulator obtained an SNR of 86.63 dB, an SNDR of 86.46 dB and an ENOB of 14.07 bits. Finally, the extraction of the initial parameters for the amplifier design proved to be satisfactory, since the modulator performance results were within the specified in the design.
{"title":"High-Level Design of a 14-bit Continuous-Time Sigma-Delta Modulator with FIR DAC for Low-Voltage Audio Devices","authors":"Matheus Cortez, A. Girardi, P. Aguirre","doi":"10.1109/SBCCI55532.2022.9893239","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893239","url":null,"abstract":"Currently, mobile and wearable devices have digital audio signal processing capabilities. Since the nature of audio signals is analog, there is a need to use analog-to-digital converters (ADCs) with high-resolution for a high signal-to-noise ratio audio acquisition. This paper presents the high-level design of a continuous-time third-order sigma-delta modulator with a FIR DAC for audio devices, using a supply voltage of 0.5 V. The design is carried out using the Delta-sigma toolbox and a discrete-time to continuous-time (DT-CT) transformation. It was estimated that the first-integrator amplifier needs a gain of 50 dB, a GBW of 5 MHz and a slew-rate of at least $3 mathrm{V}/mu mathrm{s}$. By implementing this amplifier in VerilogA and performing a transient simulation with noise, the modulator obtained an SNR of 86.63 dB, an SNDR of 86.46 dB and an ENOB of 14.07 bits. Finally, the extraction of the initial parameters for the amplifier design proved to be satisfactory, since the modulator performance results were within the specified in the design.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130772972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-22DOI: 10.1109/SBCCI55532.2022.9893249
A. Ballo, A. D. Grasso, M. Privitera
This paper introduces a design strategy for common-gate comparators, as the widely implemented comparators in active rectification systems. The method is based on the $g_{m}/I_{D}$ technique and it embraces both the power conversion efficiency of the whole system and large signal performance parameters, such as the slew-rate. As an example, the proposed strategy has been adopted to design the comparator in a power management integrated circuit for energy harvesting in fully battery-less implantable medical devices. The overall performances of the rectifier are shown, giving out a post-layout power conversion efficiency higher than 92.5%.
{"title":"A Design Procedure for Sizing Comparators in Active Rectifiers using $g_{m}/I_{D}$ Technique","authors":"A. Ballo, A. D. Grasso, M. Privitera","doi":"10.1109/SBCCI55532.2022.9893249","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893249","url":null,"abstract":"This paper introduces a design strategy for common-gate comparators, as the widely implemented comparators in active rectification systems. The method is based on the $g_{m}/I_{D}$ technique and it embraces both the power conversion efficiency of the whole system and large signal performance parameters, such as the slew-rate. As an example, the proposed strategy has been adopted to design the comparator in a power management integrated circuit for energy harvesting in fully battery-less implantable medical devices. The overall performances of the rectifier are shown, giving out a post-layout power conversion efficiency higher than 92.5%.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124066979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-22DOI: 10.1109/SBCCI55532.2022.9893219
Roberta Palau, Wagner Penny, J. Goebel, Eduardo Zummach, G. Corrêa, M. Porto, L. Agostini
This paper presents the first dedicated hardware design in the literature for the Separable Symmetric Normalized Wiener Filter (SSNWF) targeting the decoder of the AOM Video 1 (AV1) video format. The SSNWF is one of the last filters into the decoding filtering loop, being part of the Switchable Loop Restoration Filter (SLRF). The SLRF is the main novelty introduced by AV1 in the in-loop filtering process. It is used to attenuate the blurring artifacts, improving the subjective video quality and the coding efficiency. The developed hardware design presented in this paper targets the AV1 decoder and it can process Ultra-High Definition (UHD) videos with 3840x2160 pixels per frame at 60 frames per second (fps) when running at 207.03 MHz. The architecture was synthesized to standard cells using the 40 nm TSMC library, reaching an area of 37.78 Kgates and a power dissipation of 26.36 mW.
本文提出了针对AOM Video 1 (AV1)视频格式解码器的可分离对称归一化维纳滤波器(SSNWF)的专用硬件设计。SSNWF是解码滤波环路中最后的滤波器之一，是可切换环路恢复滤波器(SLRF)的一部分。SLRF是AV1在环内滤波过程中引入的主要新颖之处。该算法用于减弱模糊伪影，提高主观视频质量和编码效率。本文所开发的硬件设计以AV1解码器为目标，在207.03 MHz工作频率下，能够以60帧/秒的速度处理3840x2160像素/帧的超高清视频。利用40 nm TSMC库将该结构合成为标准单元，面积达到37.78 Kgates，功耗为26.36 mW。
{"title":"Hardware Design for the Separable Symmetric Normalized Wiener Filter of the AV1 Decoder","authors":"Roberta Palau, Wagner Penny, J. Goebel, Eduardo Zummach, G. Corrêa, M. Porto, L. Agostini","doi":"10.1109/SBCCI55532.2022.9893219","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893219","url":null,"abstract":"This paper presents the first dedicated hardware design in the literature for the Separable Symmetric Normalized Wiener Filter (SSNWF) targeting the decoder of the AOM Video 1 (AV1) video format. The SSNWF is one of the last filters into the decoding filtering loop, being part of the Switchable Loop Restoration Filter (SLRF). The SLRF is the main novelty introduced by AV1 in the in-loop filtering process. It is used to attenuate the blurring artifacts, improving the subjective video quality and the coding efficiency. The developed hardware design presented in this paper targets the AV1 decoder and it can process Ultra-High Definition (UHD) videos with 3840x2160 pixels per frame at 60 frames per second (fps) when running at 207.03 MHz. The architecture was synthesized to standard cells using the 40 nm TSMC library, reaching an area of 37.78 Kgates and a power dissipation of 26.36 mW.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129158887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-22DOI: 10.1109/SBCCI55532.2022.9893258
M. Sartori, W. Nunes, Ney Laert Vilar Calazans
Robustness to variations is desirable in current digital circuit design techniques. Sources of variations are many, and the evolution of current integrated circuit fabrication technologies does increase the amount of such sources and the complexity of ensuring circuit robustness against them. Some design paradigms naturally counter variations to one or more variation sources. Asynchronous quasi-delay insensitive design is such a paradigm, providing robustness to process, supply voltage, temperature, ageing and IR drop variations. This paper proposes an enhancement to Pulsar, a recently proposed open source automated flow for the design of quasi-delay insensitive circuits. A new set of abstract components enables the description of choices and decisions about the flow of data tokens inside asynchronous circuits. These components are now available to be used in the design capture phase of Pulsar. To build circuit cells that implement the abstract (synthesis-enabled) components, this paper brings the proposal of the handshaking mutex (HM), a versatile complex gate that eases the design of asynchronous arbiters. Results demonstrate the new flow is more powerful than the baseline version, enabling the automated synthesis of complex asynchronous circuits.
{"title":"Enhancing an Asynchronous Circuit Design Flow to Support Complex Digital System Design","authors":"M. Sartori, W. Nunes, Ney Laert Vilar Calazans","doi":"10.1109/SBCCI55532.2022.9893258","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893258","url":null,"abstract":"Robustness to variations is desirable in current digital circuit design techniques. Sources of variations are many, and the evolution of current integrated circuit fabrication technologies does increase the amount of such sources and the complexity of ensuring circuit robustness against them. Some design paradigms naturally counter variations to one or more variation sources. Asynchronous quasi-delay insensitive design is such a paradigm, providing robustness to process, supply voltage, temperature, ageing and IR drop variations. This paper proposes an enhancement to Pulsar, a recently proposed open source automated flow for the design of quasi-delay insensitive circuits. A new set of abstract components enables the description of choices and decisions about the flow of data tokens inside asynchronous circuits. These components are now available to be used in the design capture phase of Pulsar. To build circuit cells that implement the abstract (synthesis-enabled) components, this paper brings the proposal of the handshaking mutex (HM), a versatile complex gate that eases the design of asynchronous arbiters. Results demonstrate the new flow is more powerful than the baseline version, enabling the automated synthesis of complex asynchronous circuits.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123083530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-22DOI: 10.1109/SBCCI55532.2022.9893226
Peng Chen, C. Lin, Wen-Hsiao Peng
This paper presents a study of motion coding schemes for learned video compression. Most learned video compression systems explicitly signal optical flow maps to characterize motion between video frames for motion compensation. The flow maps, usually of the same size as the video frames, represent a considerable portion of the compressed bitstream. This work studies several schemes to make a non-linear prediction of the flow maps for efficient motion coding. These include signaling an incremental flow map between a coding frame and a motion-compensated frame derived from the flow map predictor. In forming the flow map predictor, we propose a learned motion extrapolation module and a motion forward warping scheme. They are further incorporated into two novel approaches, termed double warping and frame synthesis with motion forward warping, in creating an inter-frame predictor by combining the incremental flow and the flow map predictor. Extensive experiments are conducted to analyze the merits and faults of these variants, and demonstrate their superiority to predictive motion coding and intra motion coding.
{"title":"A Study of Motion Coding Schemes for Learned Video Compression","authors":"Peng Chen, C. Lin, Wen-Hsiao Peng","doi":"10.1109/SBCCI55532.2022.9893226","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893226","url":null,"abstract":"This paper presents a study of motion coding schemes for learned video compression. Most learned video compression systems explicitly signal optical flow maps to characterize motion between video frames for motion compensation. The flow maps, usually of the same size as the video frames, represent a considerable portion of the compressed bitstream. This work studies several schemes to make a non-linear prediction of the flow maps for efficient motion coding. These include signaling an incremental flow map between a coding frame and a motion-compensated frame derived from the flow map predictor. In forming the flow map predictor, we propose a learned motion extrapolation module and a motion forward warping scheme. They are further incorporated into two novel approaches, termed double warping and frame synthesis with motion forward warping, in creating an inter-frame predictor by combining the incremental flow and the flow map predictor. Extensive experiments are conducted to analyze the merits and faults of these variants, and demonstrate their superiority to predictive motion coding and intra motion coding.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116733097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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