{"title":"ESD robust 800V SCR-JFET with p+ ballast structure","authors":"S. Fujiwara, R. Burton","doi":"10.1109/EOSESD.2016.7592524","DOIUrl":null,"url":null,"abstract":"ESD robustness enhancement study of an 800V JFET including the SCR structure is conducted. A p+ ballast structure is introduced in the device and ESD robustness improvement is demonstrated with 3D TCAD simulations. Based on the TCAD study results, a ballasted device is fabricated and improved ESD performance is successfully obtained.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EOSESD.2016.7592524","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
ESD robustness enhancement study of an 800V JFET including the SCR structure is conducted. A p+ ballast structure is introduced in the device and ESD robustness improvement is demonstrated with 3D TCAD simulations. Based on the TCAD study results, a ballasted device is fabricated and improved ESD performance is successfully obtained.
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