Hardware Implementation of the Reverse Conversion RNS-WNS on FPGA

Abstract

The Residue Number System is a modern powerful tool for solving a number of specialized tasks: digital signal processing, cryptography, increasing reliability, accelerating computations, etc. The effectiveness of its use largely depends on the solution of the problem of reducing the delay and area costs for the reverse conversion of numerical data to the weighted number system. The paper considers the main methods of reverse conversion from the residue number system to the weighted number system. Their hardware implementation on FPGA and a comparative analysis are presented.