A subnanosecond HEMT 1Kb SRAM

Abstract

HIGH-SPEED LSIs have been required for high performance mainframe computers. The development of High Electron Mobility Transistor (HEMT)’ is felt to be applicable for high-speed logic operations. This paper will report on the design of a I K x l b fully static RAM using HEMT. The RAM was constructed with Enhancement/Depletion (E/D) type DCFL circuitry, using 1 . 5 ~ gate devices, and 3pm line process. The memory cell size measures 55 x 3 9 p , and the chip size is 3.0 x 2.9mm. Address access time of 0.911s and an operating power of 360mW at liquid nitrogen temperature have been obtained. A photomicrograph of the RAM is shown in Figure 1. The RAM is organized into 1024 word x lb , and arranged as a 32 x 32 matrix. Using a depletion type HEMT for load devices, E/D type DCFL circuits were employed as the basic circuit. The memory cell is a 6-transistor cross-coupled flipflop circuit with switching devices having gate lengths of 2.Opm. For peripheral circuits, 1 . 5 p gate switching device was chosen for performance reasons, and long gate devices were used as load devices. The circuit diagram of the RAM is shown in Figure 2. To obtain a high-speed operation, sufficiently large operating current was assigned to peripheral circuits, especially to the address buffer, word driver, and output buffer which have large wiring capacitances. As a result, the entire peripheral circuit which has 15% of the total device count, dissipates 85% of the chip dissipation power. As seen in Figure 1, the total area of the peripheral circuits is same as the cell array. But no particular power-down technique was employed in this design. A differential amplifier type sensing circuit and a bit line pull-up scheme were adopted to fetch data in short time from the low power memory cell. To drive large off-chip capacitance quickly, a four-stage output buffer amplifier was used with a final stage of a push-pull type output circuit constructed of high-current enhancement type devices. To obtain