Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction Technique

Abstract

This paper presents a response inversion scan cell (RISC) technique to reduce the peak capture power in test mode. The RISC technique inverts the data input of selected scan cells so that peak capture power is reduced. According to the experimental data on ISCAS'89 benchmark circuits, the RISC technique effectively reduces the peak capture power by 45% at a cost of 7.6% area overhead. The presented technique requires minimum change in the existing design for testability (DFT) methodology and it does not degrade fault coverage. The RISC technique is validated by a chip experiment on a 0.18 mum low power design.