Comprehensive study on reliability of chip-package interaction using Cu pillar joint onto low k chip

Abstract

Cu pillar technology can cater for high I/O, fine pitch and further miniaturization requirements compared to wire bonding and conventional flip chip technologies. However, chip-package interaction (CPI) for low-k chip is a critical challenge for Cu pillar technology under assembly process and temperature loading due to stiffer Cu pillar structure compared to conventional C4 bump. Thermo-compression bonding (TCB) process was developed and used for fine pitch Cu pillar assembly on Cu/low-k chip to reduce the package warpage and low-k stress. In this study, a novel TCB process modeling methodology using a 2D axisymmetry model with global-local technique was established by considering process condition step by step. The simulation results show that TCB process results in much lower package warpage and low-k stress compared to reflow process. Based on the developed TCB modeling method, the comprehensive parametric studies were conducted to optimize TCB process condition and Cu pillar design for CPI reliability improvement, including Cu pillar structure design, package geometry, and packaging materials selection. The final package and assembly solution was successfully achieved based on suggestions and recommendations provided by numerical simulation results.