Systolic array implementation of a low frequency digital oscillator

Abstract

A bit-level systolic array is presented for the implementation of a digital sinusoidal oscillator with low-frequency and low-amplitude sensitivities and low-roundoff noise. The oscillator is derived from a lossless digital two-port and is extremely suitable for low-frequency applications where conventional direct form and coupled form oscillators fail to produce comparable performances. The resultant systolic array is based on the use of a signed-digital number representation bit-level pipelined multiplier and the overall array architecture is suitable for VLSI implementation.<>