Cellular scan test generation for sequential circuits

Abstract

The authors re-examine the concept of test machine embedding and present a new test machine architecture: cellular scan. Unlike the traditional scan machine architecture, the cellular scan machine requires no scan-out pin. A dynamic scan test generation algorithm, DYNASTEE, is introduced. It reduces test sequence length when compared to existing static test generation algorithms for scan architectures. It is shown that test sequence length can be minimized further by re-ordering the scan chain.<>