{"title":"G-32-a high performance VSLI 3-D computer","authors":"L. Carr, R. Kibler, S. Hippen, T. Gargrave","doi":"10.1109/HICSS.1989.47152","DOIUrl":null,"url":null,"abstract":"A 3-D computer is characterized by sufficient speed of CPU computation, high I/O throughput, and an efficient interrupt-handling capability. The architecture of a high-performance 32-bit three-dimensional (3-D) computer, based on a custom-designed VSLI chip set is described. The G-32 consists of a single-board CPU, up to two single-board dual-bus input/output sequencers, and a memory subsystem expandable from 2 to 256 Mbytes. Up to four CPUs and four sequencers can be configured together in a multiprocessor system. The G-32 system is intended for use in real-time, time-sharing processing applications. It uses advanced high-performance CMOS gate arrays and standard cell devices. Floating-point operations have been improved with the addition of a hardware accelerator.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HICSS.1989.47152","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A 3-D computer is characterized by sufficient speed of CPU computation, high I/O throughput, and an efficient interrupt-handling capability. The architecture of a high-performance 32-bit three-dimensional (3-D) computer, based on a custom-designed VSLI chip set is described. The G-32 consists of a single-board CPU, up to two single-board dual-bus input/output sequencers, and a memory subsystem expandable from 2 to 256 Mbytes. Up to four CPUs and four sequencers can be configured together in a multiprocessor system. The G-32 system is intended for use in real-time, time-sharing processing applications. It uses advanced high-performance CMOS gate arrays and standard cell devices. Floating-point operations have been improved with the addition of a hardware accelerator.<>