{"title":"A 1-V low power rail-to-rail analog CMOS multi-function filter with configurable capability","authors":"Y. Hung, Bin-Da Liu","doi":"10.1109/APASIC.2000.896922","DOIUrl":null,"url":null,"abstract":"In this paper, a multiple function filter with configurable capability for 1-V supply voltage is proposed. The circuit can find a rank order among a set of input voltages by setting different binary signals. Moreover without modifying the circuit, the WTA/k-WTA, maximum, minimum and medium function can be easily configured. The circuit has been designed using 0.5 /spl mu/m 2P2M CMOS technology. Seven input voltages are used to verify the performance of the circuit. The results of HSPICE simulation show that the operating speed of the circuit is 2 /spl mu/s for each rank-order operation, that the input dynamic range is rail-to-rail, and that the resolution is 10 mV for 1 V supply voltage. The static power dissipation of the circuit is 11 /spl mu/W.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.2000.896922","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this paper, a multiple function filter with configurable capability for 1-V supply voltage is proposed. The circuit can find a rank order among a set of input voltages by setting different binary signals. Moreover without modifying the circuit, the WTA/k-WTA, maximum, minimum and medium function can be easily configured. The circuit has been designed using 0.5 /spl mu/m 2P2M CMOS technology. Seven input voltages are used to verify the performance of the circuit. The results of HSPICE simulation show that the operating speed of the circuit is 2 /spl mu/s for each rank-order operation, that the input dynamic range is rail-to-rail, and that the resolution is 10 mV for 1 V supply voltage. The static power dissipation of the circuit is 11 /spl mu/W.