A. Burdass, G. Campbell, R. Grisenthwaite, D. Gwilt, P. Harrod, R. York
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引用次数: 3
Abstract
This paper compares and contrast two very different approaches to testing cached CPU macrocells that are typically embedded in a System on Chip (SoC). One uses a test bus to apply functional vectors, while the other uses a combination of scan insertion, memory BIST and test collars. IP protection issues and nonintrusive tracing are also discussed.
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