Sub-clock Digital Delay for Radar Target Simulation

Abstract

Simulation of an artificial target is essential for developing and evaluating systems based on radar sensors. The simulation usually covers three fundamental principles. Signal delaying to simulate the target in a certain distance. Frequency shifting to give the target a speed according to the Doppler phenomenon. Moreover, adjusting signal magnitude to mimic the Radar cross-section (RCS) of the simulated object. For digital Radar Target Simulation, the tiniest step in signal delaying is determined by the clock period. This paper presents an idea of how to implement sub-clock period signal delaying to increase delay resolution. The idea is evaluated on FPGA based target simulator.