Spatial yield modeling for semiconductor wafers

Abstract

The distribution of good and bad chips on a semiconductor wafer typically results in two types of regions, one that contains both good and bad chips distributed in a random fashion, called a "non-zero yield region", and the other that contains almost all bad chips, called a "zero yield region". The yield of a non-zero yield region is modeled by well understood expressions derived from Poisson or negative binomial statistics. To account for yield loss associated with zero yield regions, the yield expression for non-zero yield regions is multiplied by Y/sub 0/, the fraction of the wafer occupied by non-zero yield regions. The presence, extent, and nature of zero yield regions on a given wafer provide information about yield loss mechanisms responsible for causing them. Two statistical methods are developed to detect the presence of zero yield regions and calculate Y/sub 0/ for a given wafer. These methods are based on a set-theoretic image analysis tool, called the Aura Framework, and on hypothesis testing on nearest neighbors of bad chips. Results show that the modeling of the distribution of good and bad chips on wafers in terms of zero and non-zero yield regions is highly accurate. The detection of zero yield regions provides improved insight into the yield loss mechanisms. Also, the ability to calculate Y/sub 0/ enables better evaluation of the yield models used to predict the yield of non-zero yield regions.