Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484329
M. Gallagher, C. Ebel, G. MacDougall, T. Weeks
This paper describes a borderless contact process from metal to polysilicon and diffusion regions using a unique, three-step reactive ion etch (RIE) being used on IBM's advanced semiconductor logic products at its Microelectronics Division manufacturing facility in Essex Junction, Vermont. Borderless contacts to polysilicon and diffusion allow metalization to partially spread to adjacent oxide spacer and oxide isolation regions with no adverse effects. A fast, nonselective etch begins the process by removing 8% phosphosilicate oxide (PSG) quickly for high wafer throughput. This is followed by a PSG etch that is nonselective to a nitride etch-stop layer. Optical emission at 387 nm from a nitride radical is used to endpoint this selective etch. Finally, a timed, in-situ nitride removal step opens up both polysilicon and diffusion features for metal deposition. The process window is grossly defined by over- and under-etching, resulting in junction leakage and contact opens, respectively. We will show how to predict the process window based on PSG/nitride etch rate selectivity, film thicknesses and the topography.
{"title":"A novel, borderless metal-to-diffusion contact technique","authors":"M. Gallagher, C. Ebel, G. MacDougall, T. Weeks","doi":"10.1109/ASMC.1995.484329","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484329","url":null,"abstract":"This paper describes a borderless contact process from metal to polysilicon and diffusion regions using a unique, three-step reactive ion etch (RIE) being used on IBM's advanced semiconductor logic products at its Microelectronics Division manufacturing facility in Essex Junction, Vermont. Borderless contacts to polysilicon and diffusion allow metalization to partially spread to adjacent oxide spacer and oxide isolation regions with no adverse effects. A fast, nonselective etch begins the process by removing 8% phosphosilicate oxide (PSG) quickly for high wafer throughput. This is followed by a PSG etch that is nonselective to a nitride etch-stop layer. Optical emission at 387 nm from a nitride radical is used to endpoint this selective etch. Finally, a timed, in-situ nitride removal step opens up both polysilicon and diffusion features for metal deposition. The process window is grossly defined by over- and under-etching, resulting in junction leakage and contact opens, respectively. We will show how to predict the process window based on PSG/nitride etch rate selectivity, film thicknesses and the topography.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121083528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484340
T. Harris, M.G. Ridens, B.P. Singh, E. Baaklini
Summary form only given, as follows. Discusses waferless job creation, which need not wait for wafer processing and therefore permits elimination of metrology associate delays during new product introduction. At Motorola's MOS-12 facility, implementation of waferless job creation on CD, overlay, and film thickness measurement tools has reduced new product introduction time by 2 days. In addition, because of standardization of metrology structures, there is much greater consistency in measurements across multiple products. The key components for successfully achieving waferless set up of metrology jobs are standardizing metrology in scribe structures, incorporating specialized inscribe pattern recognition features, tightly matching machines, and directly manipulating job plans. By having standard CAD libraries for each type of measurement the coordinates of all measurement features are known. By using optimized in scribe pattern recognition features, target images can be reused on new products. Tight matching of machines permits job plans written on one machine to be copied to all similar machines without modification. Direct manipulation of job plans eliminates the need for a wafer during job creation.
{"title":"Waferless metrology job creation","authors":"T. Harris, M.G. Ridens, B.P. Singh, E. Baaklini","doi":"10.1109/ASMC.1995.484340","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484340","url":null,"abstract":"Summary form only given, as follows. Discusses waferless job creation, which need not wait for wafer processing and therefore permits elimination of metrology associate delays during new product introduction. At Motorola's MOS-12 facility, implementation of waferless job creation on CD, overlay, and film thickness measurement tools has reduced new product introduction time by 2 days. In addition, because of standardization of metrology structures, there is much greater consistency in measurements across multiple products. The key components for successfully achieving waferless set up of metrology jobs are standardizing metrology in scribe structures, incorporating specialized inscribe pattern recognition features, tightly matching machines, and directly manipulating job plans. By having standard CAD libraries for each type of measurement the coordinates of all measurement features are known. By using optimized in scribe pattern recognition features, target images can be reused on new products. Tight matching of machines permits job plans written on one machine to be copied to all similar machines without modification. Direct manipulation of job plans eliminates the need for a wafer during job creation.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128980688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484361
W.M. Evans, R. Cyr, D. Wilson
Yield loss detected at electrical test is attributable to various factors in the fabrication of semiconductor devices. The accurate partitioning of this yield loss to the appropriate tool or process segment is necessary for rapid yield improvements. In this paper we discuss a method of partitioning that uses production test patterns and associated critical areas. We discuss the calculation of critical area as used in this paper, as well as methods for determining relevant test pattern structures that relate to the product. This model relies on full loop test patterns designed to maximize the available information for micro yield modeling. This method has been used successfully in new product yield enhancement activities for bipolar products at NSFM. The partitioning starts with a division between systematic and random components as a result of wafer map analysis. We give an algorithm for determining the division of systematic and random components based on the wafermap (Sort) data. The random components are then broken down into various front-end (leakage) and backend (metal) issues. Although no validation has been made regarding the accuracy of the partition, the combined model has shown a greater than 90% correlation to reality over a high intensity ramp period of several months.
{"title":"Partitioning yield loss via test pattern structures and critical areas","authors":"W.M. Evans, R. Cyr, D. Wilson","doi":"10.1109/ASMC.1995.484361","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484361","url":null,"abstract":"Yield loss detected at electrical test is attributable to various factors in the fabrication of semiconductor devices. The accurate partitioning of this yield loss to the appropriate tool or process segment is necessary for rapid yield improvements. In this paper we discuss a method of partitioning that uses production test patterns and associated critical areas. We discuss the calculation of critical area as used in this paper, as well as methods for determining relevant test pattern structures that relate to the product. This model relies on full loop test patterns designed to maximize the available information for micro yield modeling. This method has been used successfully in new product yield enhancement activities for bipolar products at NSFM. The partitioning starts with a division between systematic and random components as a result of wafer map analysis. We give an algorithm for determining the division of systematic and random components based on the wafermap (Sort) data. The random components are then broken down into various front-end (leakage) and backend (metal) issues. Although no validation has been made regarding the accuracy of the partition, the combined model has shown a greater than 90% correlation to reality over a high intensity ramp period of several months.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129076409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484408
G. Kong, C. Stager, A. C. Campbell
The implementation of an in-situ particle monitor (ISPM) on a high volume manufacturing oxide plasma etcher is discussed. Plasma process generated particles have been traditionally monitored using the Particle per Wafer Pass (PWP) methodology, using test wafers and a particle inspection system. As equipment throughputs continue to increase, more PWP test wafer runs are needed to maintain a quick response to sudden high particle events. Increasing the number of test wafer runs not only increases test wafer cost, but also reduces equipment availability and increases cost of ownership. The ISPM allows real-time response to high particle events, better understanding of equipment and process particulate status, reduced defectivity, increased tool availability, and reduced cost of ownership. An oxide plasma etching system was used in this investigation to collect a large data base of ISPM data. Strong correlation was established between regular PWP and ISPM data during RF-plasma on events. The ISPM was also demonstrated to provide valuable insights into the particle deposition mechanism. The initial particle counts were found to stay constant over a long duration of the equipment run time. However, when the PWP count started to increase, the ISPM signal increased sharply. Moreover, the frequency of high particle counts was observed to increase as the equipment run time increased. Finally, a process comparison based on the ISPM is discussed. Based on the correlation to PWP methodology, the increased data collection capability and potential reduction in cost of ownership, the ISPM has been implemented in the manufacturing line.
{"title":"Implementation of an in-situ particle monitor system on an oxide plasma process system","authors":"G. Kong, C. Stager, A. C. Campbell","doi":"10.1109/ASMC.1995.484408","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484408","url":null,"abstract":"The implementation of an in-situ particle monitor (ISPM) on a high volume manufacturing oxide plasma etcher is discussed. Plasma process generated particles have been traditionally monitored using the Particle per Wafer Pass (PWP) methodology, using test wafers and a particle inspection system. As equipment throughputs continue to increase, more PWP test wafer runs are needed to maintain a quick response to sudden high particle events. Increasing the number of test wafer runs not only increases test wafer cost, but also reduces equipment availability and increases cost of ownership. The ISPM allows real-time response to high particle events, better understanding of equipment and process particulate status, reduced defectivity, increased tool availability, and reduced cost of ownership. An oxide plasma etching system was used in this investigation to collect a large data base of ISPM data. Strong correlation was established between regular PWP and ISPM data during RF-plasma on events. The ISPM was also demonstrated to provide valuable insights into the particle deposition mechanism. The initial particle counts were found to stay constant over a long duration of the equipment run time. However, when the PWP count started to increase, the ISPM signal increased sharply. Moreover, the frequency of high particle counts was observed to increase as the equipment run time increased. Finally, a process comparison based on the ISPM is discussed. Based on the correlation to PWP methodology, the increased data collection capability and potential reduction in cost of ownership, the ISPM has been implemented in the manufacturing line.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123352023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484382
E. Wang, R. Akella
We consider performance modeling of yield learning in semiconductor manufacturing. Attention is restricted to the learning of defect reduction in the wafer fabrication stage of IC production. The performance measures of primary interest are the rate of yield improvement and the return on investment for defect reduction strategies. Based on the inputs from fabs, we describe the defect reduction process and learning cycle, and model it to optimize the economic benefits of fast yield improvement. Potential approaches to analyze the model are proposed. We discuss the impact of resources deployed for yield learning on fab performance.
{"title":"Resource allocation for yield learning in semiconductor manufacturing","authors":"E. Wang, R. Akella","doi":"10.1109/ASMC.1995.484382","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484382","url":null,"abstract":"We consider performance modeling of yield learning in semiconductor manufacturing. Attention is restricted to the learning of defect reduction in the wafer fabrication stage of IC production. The performance measures of primary interest are the rate of yield improvement and the return on investment for defect reduction strategies. Based on the inputs from fabs, we describe the defect reduction process and learning cycle, and model it to optimize the economic benefits of fast yield improvement. Potential approaches to analyze the model are proposed. We discuss the impact of resources deployed for yield learning on fab performance.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124102152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484344
E. E. Chain, T. Harris, B.P. Singh, T. Nagy, W. Merkel
As device linewidths shrink to 0.5 /spl mu/m and below the ECD (Electrical Critical Dimension) measurement technique is the best choice for conducting substrates. In this size regime, ECD is poised to replace SEM (Scanning Electron Microscope) as the standard tool of the semiconductor industry, with a measurement capability significantly better than that of the CD SEM. Keithley Instruments has developed an advanced electrical prober for use at Motorola's MOS-12 facility. This tool provides in-line CD measurements in a completely automated, hands-off "load-and-go" mode that requires only wafer loading, measurement recipe loading, and a "run" command for processing. Its expected capability will permit measurement of lines thinner than 0.5 /spl mu/m with a good accuracy, and with complete data transfer to the factory data collection and analysis system upon measurement completion. Results on the repeatability and reproducibility of fully automated measurements are presented, together with correlation to SEM measurements.
{"title":"In-line electrical probe for CD metrology below 0.5 /spl mu/m","authors":"E. E. Chain, T. Harris, B.P. Singh, T. Nagy, W. Merkel","doi":"10.1109/ASMC.1995.484344","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484344","url":null,"abstract":"As device linewidths shrink to 0.5 /spl mu/m and below the ECD (Electrical Critical Dimension) measurement technique is the best choice for conducting substrates. In this size regime, ECD is poised to replace SEM (Scanning Electron Microscope) as the standard tool of the semiconductor industry, with a measurement capability significantly better than that of the CD SEM. Keithley Instruments has developed an advanced electrical prober for use at Motorola's MOS-12 facility. This tool provides in-line CD measurements in a completely automated, hands-off \"load-and-go\" mode that requires only wafer loading, measurement recipe loading, and a \"run\" command for processing. Its expected capability will permit measurement of lines thinner than 0.5 /spl mu/m with a good accuracy, and with complete data transfer to the factory data collection and analysis system upon measurement completion. Results on the repeatability and reproducibility of fully automated measurements are presented, together with correlation to SEM measurements.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125248874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484392
S. D. Hossain, M. Paś, R. Cleavelin, R. Robinson, G. Miner, A. Nanda
A model is presented for an intra semiconductor user-equipment supplier-SEMATECH project effort. The on-going 0.25 /spl mu/m Source/Drain Rapid Thermal Process (S/D RTP) project is used as the basis for this model. The successful completion of this project supports the model's assertions. A methodological approach taken from the initial stages of a project to the completion generates valuable and valid data, provides a planned strategy, allows for timely allocation of resources, and results in a win-win situation for all involved. This model will be referred to as "Model for Supplier/User Partnering" or MSUP.
{"title":"A model for intra industry, supplier, and SEMATECH collaboration including an inter-group effort by industry","authors":"S. D. Hossain, M. Paś, R. Cleavelin, R. Robinson, G. Miner, A. Nanda","doi":"10.1109/ASMC.1995.484392","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484392","url":null,"abstract":"A model is presented for an intra semiconductor user-equipment supplier-SEMATECH project effort. The on-going 0.25 /spl mu/m Source/Drain Rapid Thermal Process (S/D RTP) project is used as the basis for this model. The successful completion of this project supports the model's assertions. A methodological approach taken from the initial stages of a project to the completion generates valuable and valid data, provides a planned strategy, allows for timely allocation of resources, and results in a win-win situation for all involved. This model will be referred to as \"Model for Supplier/User Partnering\" or MSUP.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131341045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484339
A. Diebold
During 1994, the Semiconductor Industry Association developed and issued the second integrated circuit manufacturing roadmap: The National Technology Roadmap for Semiconductors (NTRS). Metrology requirements cut across the boundaries of materials and bulk processes (transistor fabrication processes), lithography, interconnect, design and electrical test, and factory integration. In the NTRS, Metrology is referred to as a cross-cut requirement and specific needs can be found in the technology sections. In order to supplement the NTRS, a Metrology Roadmap was published by SEMATECH. The roadmap was developed by representatives from the SEMATECH member companies, NIST, Sandia, and metrology tool suppliers. The measurement requirements in the Metrology Roadmap are taken directly from the NTRS, i.e., the timeline for gate dielectric thickness vs. technology generation. The author provides an overview of the Metrology Roadmap and discusses key trends such as the move toward real time process control.
{"title":"Overview of metrology requirements based on the 1994 National Technology Roadmap for semiconductors","authors":"A. Diebold","doi":"10.1109/ASMC.1995.484339","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484339","url":null,"abstract":"During 1994, the Semiconductor Industry Association developed and issued the second integrated circuit manufacturing roadmap: The National Technology Roadmap for Semiconductors (NTRS). Metrology requirements cut across the boundaries of materials and bulk processes (transistor fabrication processes), lithography, interconnect, design and electrical test, and factory integration. In the NTRS, Metrology is referred to as a cross-cut requirement and specific needs can be found in the technology sections. In order to supplement the NTRS, a Metrology Roadmap was published by SEMATECH. The roadmap was developed by representatives from the SEMATECH member companies, NIST, Sandia, and metrology tool suppliers. The measurement requirements in the Metrology Roadmap are taken directly from the NTRS, i.e., the timeline for gate dielectric thickness vs. technology generation. The author provides an overview of the Metrology Roadmap and discusses key trends such as the move toward real time process control.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125203354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484388
M. Breeze, J. Davies
For many years industry gurus have been urging closer links between suppliers and customers. At the Intel Fab 10 facility in Ireland, we believe this concept has been taken further than ever before in the semiconductor industry, via the Supplier Support Program. Intel's Fab 10 facility does not follow the traditional Fab support structure, in that it has substituted supplier personnel to carry out the equipment engineering functions. The performance of the overall system in expediting the turn on of Intel's billion dollar Pentium fab is discussed with respect to factory ramp time, the changing phases of the program and the consequences and expectations on line yield and die yield.
{"title":"A shared approach to wafer fab support","authors":"M. Breeze, J. Davies","doi":"10.1109/ASMC.1995.484388","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484388","url":null,"abstract":"For many years industry gurus have been urging closer links between suppliers and customers. At the Intel Fab 10 facility in Ireland, we believe this concept has been taken further than ever before in the semiconductor industry, via the Supplier Support Program. Intel's Fab 10 facility does not follow the traditional Fab support structure, in that it has substituted supplier personnel to carry out the equipment engineering functions. The performance of the overall system in expediting the turn on of Intel's billion dollar Pentium fab is discussed with respect to factory ramp time, the changing phases of the program and the consequences and expectations on line yield and die yield.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133070975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484325
J. Cook
Summary form only given, as follows. The requirements for 0.25 /spl mu/m etch technologies are making successful dielectric etch processing more difficult to realize than ever before. The minute dimensions of the features, coupled with films of widely varying thickness (/spl ap/7000 to 20000+/spl Aring/) result in inherently narrow process windows, wherein the balance between RIE "lag" (ARDE) and selectivity to underlayers (e.g. Si/sub 3/ N/sub 4/) that are chemically similar to the film being etched but which have the added property of nonplanarity, and thus higher sputter yield. Maintaining selectivity to impurities, charge-up and particulates require that tools and processes address cleanliness, plasma uniformity and materials to degrees unthinkable until only recently. This paper describes the development of one such tool, a low pressure, inductively coupled, high density plasma system that has addressed a number of the issues arising from these advanced application etches. Among the items and issues discussed will be the underlying principals of operation, the implementation and etch results, especially on contact, self-aligned contact (SAC) and via applications. Issues affecting "manufacturability", their causes and solutions will also be addressed along with some considerations of scaling the system to 300 mm wafer sizes.
{"title":"Advanced dielectric etching with a high density plasma tool: issues and challenges in manufacturing","authors":"J. Cook","doi":"10.1109/ASMC.1995.484325","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484325","url":null,"abstract":"Summary form only given, as follows. The requirements for 0.25 /spl mu/m etch technologies are making successful dielectric etch processing more difficult to realize than ever before. The minute dimensions of the features, coupled with films of widely varying thickness (/spl ap/7000 to 20000+/spl Aring/) result in inherently narrow process windows, wherein the balance between RIE \"lag\" (ARDE) and selectivity to underlayers (e.g. Si/sub 3/ N/sub 4/) that are chemically similar to the film being etched but which have the added property of nonplanarity, and thus higher sputter yield. Maintaining selectivity to impurities, charge-up and particulates require that tools and processes address cleanliness, plasma uniformity and materials to degrees unthinkable until only recently. This paper describes the development of one such tool, a low pressure, inductively coupled, high density plasma system that has addressed a number of the issues arising from these advanced application etches. Among the items and issues discussed will be the underlying principals of operation, the implementation and etch results, especially on contact, self-aligned contact (SAC) and via applications. Issues affecting \"manufacturability\", their causes and solutions will also be addressed along with some considerations of scaling the system to 300 mm wafer sizes.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114407713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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