Device design and analysis of logic circuits and SRAMs for Germanium FinFETs on SOI and bulk substrates

Abstract

A comparative analysis of Germanium-on-Insulator FinFET (GeOI FinFET) and Germanium on bulk substrate FinFET (Ge bulk FinFET) at device and circuit level with respect to Si counterparts is presented. GeOI FinFET shows larger leakage current than Ge bulk FinFET due to the parasitic bipolar effect triggered by the band-to-band tunneling (BTBT) leakage. The effectiveness of different dual-Vt technology options including increasing channel doping, increasing gate length and drain-side underlap for leakage reduction is analyzed for GeOI and Ge bulk FinFET circuits and SRAMs. An optimum asymmetric underlap design in SRAM using asymmetric underlap pull-up and access transistors (PUAX-asym) is proposed. GeOI and Ge bulk FinFETs with asymmetric underlap design show significant improvement in leakage-delay performance and stability in logic circuits and SRAM cells.