{"title":"Ultra low-voltage current mirrors and pseudo differential pairs","authors":"Y. Berg, T. Lande","doi":"10.1109/ASIC.1998.722813","DOIUrl":null,"url":null,"abstract":"In this paper we present both novel current-mirrors and a novel pseudo differential pairs using floating-gate transistors available in standard double-poly CMOS. The circuits are modeled and simulated down to 50 mV supply voltage. Wide dynamic range combined with high linearity is achieved with Early effect compensation using minimum transistors.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1998.722813","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
In this paper we present both novel current-mirrors and a novel pseudo differential pairs using floating-gate transistors available in standard double-poly CMOS. The circuits are modeled and simulated down to 50 mV supply voltage. Wide dynamic range combined with high linearity is achieved with Early effect compensation using minimum transistors.
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