Fault modeling and pattern-sensitivity testing for a multilevel DRAM

Abstract

Multilevel dynamic random-access memory (MLDRAM) attempts to increase the storage density of semiconductor memory without further reducing the lithographic dimensions. It does so by using more than two possible signal voltages on each cell capacitor thus permitting more than one bit to be stored in each cell. Birk's MLDRAM scheme has several promising properties, including robust locally-generated data signal and reference signal generation, and fast flash-conversion sensing. This paper describes a fault model for Birk's MLDRAM that was developed by considering the behaviors produced by likely defects at the schematic level. The resulting behaviors include faults that are detectable as observable logical errors, faults that can be detected by current measurements, and faults that, in the worst case, can only be detected by testing for degraded noise margins. All Boolean faults in the fault model can be detected by an efficient test whose length grows linearly in the number of cells. The narrower noise margins in MLDRAM will make it more vulnerable to pattern sensitivities. We also developed a linear test that evaluates worst-case sensing conditions.