Fast Locking Dual Band PLL for NB-IoT with QPSK Modulation

Jae Hyung Jung, Kangyoon Lee
{"title":"Fast Locking Dual Band PLL for NB-IoT with QPSK Modulation","authors":"Jae Hyung Jung, Kangyoon Lee","doi":"10.1109/ICUFN57995.2023.10200692","DOIUrl":null,"url":null,"abstract":"This paper represents PLL (Phase Locked Loop) for dual band communication of NB-IoT and LPWAIoT, of which the Band width is 699MHz to 960MHz, 1710MHz to 2170MHz. The lock time of the PLL improved by combining the digital operation with analog when tracking the target frequency. In the proposed PLL architecture, many techniques are used to fasten lock time, to cover the wide range of the VCO (Voltage Controlled Oscillator) for the QPSK (Quaternary Phase Shift Keying) communication. The proposed PLL is designed with 65nm CMOS technology and covers the operating frequency range from 2624 MHz to 4471 MHz with a reference clock frequency of 30.72 MHz. The measured phase noise performance of the proposed PLL is 106.15 dBc/Hz at a VCO output frequency of 4.34 GHz at an offset frequency of 1MHz.","PeriodicalId":341881,"journal":{"name":"2023 Fourteenth International Conference on Ubiquitous and Future Networks (ICUFN)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 Fourteenth International Conference on Ubiquitous and Future Networks (ICUFN)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICUFN57995.2023.10200692","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

This paper represents PLL (Phase Locked Loop) for dual band communication of NB-IoT and LPWAIoT, of which the Band width is 699MHz to 960MHz, 1710MHz to 2170MHz. The lock time of the PLL improved by combining the digital operation with analog when tracking the target frequency. In the proposed PLL architecture, many techniques are used to fasten lock time, to cover the wide range of the VCO (Voltage Controlled Oscillator) for the QPSK (Quaternary Phase Shift Keying) communication. The proposed PLL is designed with 65nm CMOS technology and covers the operating frequency range from 2624 MHz to 4471 MHz with a reference clock frequency of 30.72 MHz. The measured phase noise performance of the proposed PLL is 106.15 dBc/Hz at a VCO output frequency of 4.34 GHz at an offset frequency of 1MHz.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
用于QPSK调制的NB-IoT快速锁定双频锁相环
本文介绍了用于NB-IoT和LPWAIoT双频通信的锁相环(PLL),其中带宽为699MHz ~ 960MHz, 1710MHz ~ 2170MHz。在跟踪目标频率时,将数字运算与模拟运算相结合,提高了锁相环的锁相时间。在提出的锁相环架构中,采用了许多技术来固定锁相时间,以覆盖QPSK通信的宽范围VCO(压控振荡器)。该锁相环采用65nm CMOS技术设计,工作频率范围为2624 MHz至4471 MHz,参考时钟频率为30.72 MHz。在VCO输出频率为4.34 GHz、偏移频率为1MHz时,该锁相环的相位噪声性能为106.15 dBc/Hz。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
In Search of Distance Functions That Improve Autoencoder Performance for Intrusion Detection DeepASD: Facial Image Analysis for Autism Spectrum Diagnosis via Explainable Artificial Intelligence Bimodal Speech Emotion Recognition using Fused Intra and Cross Modality Features A Study on Latency Prediction in 5G network Broadcasting in chains of rings
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1