Cost-Effective Reliable EEPROM Cell Based on Single-poly Structure

Abstract

A novel single-poly EEPROM cell composed of two PMOS transistors is presented in this paper. A PMOS tunneling transistor is utilized to enhance the reliability of the memory cell during the erase operation, and the other one is used as the coupling transistor. A minimum-sized PMOS is used to improve the capacitance coupling coefficient and saves area consumption. An additional PMOS transistor is added to each array cell to ensure high efficiency and safety. The memory cell is fabricated in a 0.5μm CMOS process. The test results show that the proposed structure can be cycled for more than 20k times under the write and erase potential of 15V with 10ms operation pulse.