Probabilistic Model Checking for Biology

M. Kwiatkowska, Chris Thachuk
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引用次数: 21

Abstract

Probabilistic model checking is an automated method for verifying the correctness and performance of probabilistic models. Property specifications are expressed in probabilistic temporal logic, denoting, for example, the probability of a given event, the probability of its occurrence within a given time interval, or expected number of times it has occurred in a time period. This chapter focuses on the application of probabilistic model checking to biological systems modelled as continuous-time Markov chains, illustrating the usefulness of these techniques through relevant case studies performed with the probabilistic model checker PRISM. We begin with an introduction to discrete-time Markov chains and the corresponding model checking algorithms. Then continuous-time Markov chain models are defined, together with the logic CSL (Continuous Stochastic Logic), and an overview of model checking for CSL is given, which proceeds mainly by reduction to discrete-time Markov chains. The techniques are illustrated with examples of biochemical reaction networks, which are verified against quantitative temporal properties. Next a biological case study analysing the Fibroblast Growth Factor (FGF) molecular signalling pathway is summarised, highlighting how probabilistic model checking can assist in scientific discovery. Finally, we consider DNA computation, and specifically the DSD formalism (DNA Strand Displacement), and show how errors can be detected in DNA gate designs, analogous to model checking for digital circuits.
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生物学的概率模型检验
概率模型检查是一种自动验证概率模型正确性和性能的方法。属性规范以概率时态逻辑表示,例如表示给定事件的概率,在给定时间间隔内发生的概率,或在一段时间内发生的预期次数。本章重点介绍了概率模型检查在连续时间马尔可夫链建模的生物系统中的应用,并通过使用概率模型检查器PRISM进行的相关案例研究说明了这些技术的实用性。我们首先介绍离散时间马尔可夫链和相应的模型检查算法。然后定义了连续时间马尔可夫链模型及其逻辑CSL (Continuous Stochastic logic,连续随机逻辑),并概述了CSL模型的检验方法,主要是将CSL模型简化为离散时间马尔可夫链。用生化反应网络的例子说明了这些技术,并对定量时间性质进行了验证。接下来,总结了一个分析成纤维细胞生长因子(FGF)分子信号通路的生物学案例研究,强调了概率模型检查如何有助于科学发现。最后,我们考虑DNA计算,特别是DSD形式化(DNA链位移),并展示如何在DNA门设计中检测错误,类似于数字电路的模型检查。
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