R. Ooi, F. Costa, Sam Hsieh, E. Chiu, Wendy Xu, Dave Yu, Darwin Fan, Allen Cheng, Andrew Gattuso, Yongfu Wang, Currey Hsieh, Jeffery Toran, J. Thompson, Pierre-Louis Toussaint, Ryan Curry, L. W. Keat, R. Kulterman, H. Fu
{"title":"High Density Interconnect (HDI) Socket Flow & Waprage Prediction & Characterization","authors":"R. Ooi, F. Costa, Sam Hsieh, E. Chiu, Wendy Xu, Dave Yu, Darwin Fan, Allen Cheng, Andrew Gattuso, Yongfu Wang, Currey Hsieh, Jeffery Toran, J. Thompson, Pierre-Louis Toussaint, Ryan Curry, L. W. Keat, R. Kulterman, H. Fu","doi":"10.1109/EPTC56328.2022.10013256","DOIUrl":null,"url":null,"abstract":"High density interconnect (HDI) sockets for CPU, GPU etc. is trending to larger form factor as the interconnect counts approach the realm of 10,000. One of the key bottleneck in HDI socket development is the ability of flow and warpage simulation techniques to reduce the design cycle time. The focus of this project is to explore novel simulation techniques to speed up the flow prediction part of simulation and reduce physical experiments needed to improve time to market (TTM) cycle of HDI sockets. The main challenge in HDI socket simulation is: (1) complexity of fibre-filled liquid crystal polymer (LCP) material properties and (2) complex but repetitive pin holes in the core pin region of the HDI socket. This takes up ~90% of the simulation time and slows down the design cycle. In this project, focus was put in to simplify the repetitive pin hole structure. The pin hole arrays are represented by equivalent flow resistant model and produce similar flow patterns in shorter time. In order to achieve this, three (3) LCP materials grades with known properties were provided by project partner Celanese. Test vehicle (TV) of HDI sockets were then build by socket fabrication partners using the LCP material provided. Room temp (RT) warpage of the socket were measured, together with short-shot samples collected for simulation flow and warpage prediction validation. The repetitive pin hole arrays of the HDI sockets are represented by equivalent flow resistant model. The predicted flow patterns from simulation are in good agreement with short-shot samples. The warpage shape and magnitude predictions are also in good agreement for 2 out of 3 material grades. It was later found out that the odd material that has different warpage has a different matrix (resin) LCP property. Solving time improvement ranging between 3.6x and 35x times were demonstrated in the proof of concept. The project outcome allows faster flow and warpage simulation for HDI socket design and development. The utilization of numerical predictions will be greatly increased, reduced material cost used for design prototyping and injection mold chase tape outs. Simulation software partners from the project will develop further on the demo beta versions for eventual product releases.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPTC56328.2022.10013256","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
High density interconnect (HDI) sockets for CPU, GPU etc. is trending to larger form factor as the interconnect counts approach the realm of 10,000. One of the key bottleneck in HDI socket development is the ability of flow and warpage simulation techniques to reduce the design cycle time. The focus of this project is to explore novel simulation techniques to speed up the flow prediction part of simulation and reduce physical experiments needed to improve time to market (TTM) cycle of HDI sockets. The main challenge in HDI socket simulation is: (1) complexity of fibre-filled liquid crystal polymer (LCP) material properties and (2) complex but repetitive pin holes in the core pin region of the HDI socket. This takes up ~90% of the simulation time and slows down the design cycle. In this project, focus was put in to simplify the repetitive pin hole structure. The pin hole arrays are represented by equivalent flow resistant model and produce similar flow patterns in shorter time. In order to achieve this, three (3) LCP materials grades with known properties were provided by project partner Celanese. Test vehicle (TV) of HDI sockets were then build by socket fabrication partners using the LCP material provided. Room temp (RT) warpage of the socket were measured, together with short-shot samples collected for simulation flow and warpage prediction validation. The repetitive pin hole arrays of the HDI sockets are represented by equivalent flow resistant model. The predicted flow patterns from simulation are in good agreement with short-shot samples. The warpage shape and magnitude predictions are also in good agreement for 2 out of 3 material grades. It was later found out that the odd material that has different warpage has a different matrix (resin) LCP property. Solving time improvement ranging between 3.6x and 35x times were demonstrated in the proof of concept. The project outcome allows faster flow and warpage simulation for HDI socket design and development. The utilization of numerical predictions will be greatly increased, reduced material cost used for design prototyping and injection mold chase tape outs. Simulation software partners from the project will develop further on the demo beta versions for eventual product releases.