A reseeding technique for LFSR-based BIST applications

Abstract

In this paper, we describe a new design methodology for LFSR-based test pattern generators (TPG). Multiple seeds are produced by the TPG itself to deal with hard-to-detect faults, and this function is achieved without using a ROM to store the seeds. A reseeding logic is incorporated in the TPG, which loads new seeds into the LFSR whenever specific states are reached. In this way, useless test vectors are skipped and thus the test application time can be greatly reduced. We experiment the design methodology by applying it to some MCNC benchmark circuits, and the results show that TPGs designed with this technique require much less hardware overhead than the previous known reseeding techniques.