Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181679
J. Hirase
Yield is a topic of great concern in VLSI manufacture. Still, conventional research results present only average values for the yield. The present paper discloses how the yield shows a beta distribution and how that yield can be evaluated by obtaining its cumulative probability. Furthermore, a method is introduced to calculate the systematic yield that can be obtained with relative ease even with the tester on-line. Finally, concrete examples are given where an improvement in the yield was accomplished through the use of this calculation method.
{"title":"High precision result evaluation of VLSI","authors":"J. Hirase","doi":"10.1109/ATS.2002.1181679","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181679","url":null,"abstract":"Yield is a topic of great concern in VLSI manufacture. Still, conventional research results present only average values for the yield. The present paper discloses how the yield shows a beta distribution and how that yield can be evaluated by obtaining its cumulative probability. Furthermore, a method is introduced to calculate the systematic yield that can be obtained with relative ease even with the tester on-line. Finally, concrete examples are given where an improvement in the yield was accomplished through the use of this calculation method.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115439830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181691
D. Xiang, Shan Gu, H. Fujiwara
A two stage non-scan design for testability method is proposed. The first stage selects test points based on an earlier testability measure conflict. A new testability measure conflict+ based on conflict analysis of hard-faults in the process of test generation is introduced, which emulates most general features of sequential ATPG. A new design for testability algorithm is proposed to select test points by using conflict+. Test points are selected in the second stage based on the hard faults after the initial ATPG run of the design for testability circuit in the preliminary stage. Effective approximation schemes are adopted to get reasonable estimation of the testability measure. Several effective techniques are adopted to accelerate the process of the proposed design for testability algorithm.
{"title":"Non-scan design for testability based on fault oriented conflict analysis","authors":"D. Xiang, Shan Gu, H. Fujiwara","doi":"10.1109/ATS.2002.1181691","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181691","url":null,"abstract":"A two stage non-scan design for testability method is proposed. The first stage selects test points based on an earlier testability measure conflict. A new testability measure conflict+ based on conflict analysis of hard-faults in the process of test generation is introduced, which emulates most general features of sequential ATPG. A new design for testability algorithm is proposed to select test points by using conflict+. Test points are selected in the second stage based on the hard faults after the initial ATPG run of the design for testability circuit in the preliminary stage. Effective approximation schemes are adopted to get reasonable estimation of the testability measure. Several effective techniques are adopted to accelerate the process of the proposed design for testability algorithm.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124410534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181714
F. Vargas, D. Lettnin, D. Brum, D. Prestes
We present a new approach to design fault tolerant artificial neural networks (ANNs). Additionally, this approach allows estimating the final network reliability. This approach is based on the mutation analysis technique and is used during the training process of the ANN. The basic idea is to train the ANN in the presence of faults (single-fault model is assumed). To do so, a set of faults is injected into the code describing the ANN. This procedure yields mutation versions of the original ANN code, which in turn are used to train the network in an iterative process with the designer until the moment when the ANN is no longer sensible to the single faults injected. In other words, the network became tolerant to the considered set of faults. A practical example where an ANN is used to recognize an electrocardiogram (ECG) and to measure ECG parameters illustrates the proposed methodology.
{"title":"A new learning approach to design fault tolerant ANNs: finally a zero HW-SW overhead","authors":"F. Vargas, D. Lettnin, D. Brum, D. Prestes","doi":"10.1109/ATS.2002.1181714","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181714","url":null,"abstract":"We present a new approach to design fault tolerant artificial neural networks (ANNs). Additionally, this approach allows estimating the final network reliability. This approach is based on the mutation analysis technique and is used during the training process of the ANN. The basic idea is to train the ANN in the presence of faults (single-fault model is assumed). To do so, a set of faults is injected into the code describing the ANN. This procedure yields mutation versions of the original ANN code, which in turn are used to train the network in an iterative process with the designer until the moment when the ANN is no longer sensible to the single faults injected. In other words, the network became tolerant to the considered set of faults. A practical example where an ANN is used to recognize an electrocardiogram (ECG) and to measure ECG parameters illustrates the proposed methodology.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"416 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120875052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181736
K. Ko, M. Wong, Yim-Shu Lee
The rapid growing trend of utilization of re-useable intellectual property (IP) cores for system-on-chip (SOC) design demands an effective, fast and efficient test scheme. This paper presents a unified approach to SOC testing that uses a built-in self-test (BIST) technique based on summations of cores' test output voltages (SOCTOV), which has the advantage of small hardware overhead and fast testing time. The proposed BIST technique is developed in conjunction with our previous proposed BIST technique which is based on weighted sums of selected node voltages (WSSNV) for embedded cores. The WSSNV BIST technique provides high fault coverage for individual cores while the SOCTOV BIST technique provides a 100% fault diagnosis resolution for locating the faulty core. It is an alternative solution to SOC testing especially when chip area overhead is a critical concern.
{"title":"Testing system-on-chip by summations of cores' test output voltages","authors":"K. Ko, M. Wong, Yim-Shu Lee","doi":"10.1109/ATS.2002.1181736","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181736","url":null,"abstract":"The rapid growing trend of utilization of re-useable intellectual property (IP) cores for system-on-chip (SOC) design demands an effective, fast and efficient test scheme. This paper presents a unified approach to SOC testing that uses a built-in self-test (BIST) technique based on summations of cores' test output voltages (SOCTOV), which has the advantage of small hardware overhead and fast testing time. The proposed BIST technique is developed in conjunction with our previous proposed BIST technique which is based on weighted sums of selected node voltages (WSSNV) for embedded cores. The WSSNV BIST technique provides high fault coverage for individual cores while the SOCTOV BIST technique provides a 100% fault diagnosis resolution for locating the faulty core. It is an alternative solution to SOC testing especially when chip area overhead is a critical concern.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124935566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181696
I. Pomeranz, S. Reddy
We describe a built-in test pattern generation method for delay faults in scan circuits based on partitioning and storage of test sets. Under this method, a precomputed test set is partitioned into several sets containing values of primary inputs or state variables. The on-chip test set is obtained by implementing the Cartesian product of the stored sets. The sizes of the sets are minimized before they are stored on-chip in order to reduce the storage requirements and the test application time. The delay fault model we consider is the transition fault model.
{"title":"A partitioning and storage based built-in test pattern generation method for delay faults in scan circuits","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/ATS.2002.1181696","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181696","url":null,"abstract":"We describe a built-in test pattern generation method for delay faults in scan circuits based on partitioning and storage of test sets. Under this method, a precomputed test set is partitioned into several sets containing values of primary inputs or state variables. The on-chip test set is obtained by implementing the Cartesian product of the stored sets. The sizes of the sets are minimized before they are stored on-chip in order to reduce the storage requirements and the test application time. The delay fault model we consider is the transition fault model.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125417575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181682
J. Savir, Zhen Guo
This paper investigates the detectability of parameter faults in linear, time-invariant, analog circuits. We show that there are inherent limitations with regard to analog faults detectability.
研究了线性时不变模拟电路中参数故障的可检测性。我们表明，在模拟故障可检测性方面存在固有的局限性。
{"title":"Test limitations of parametric faults in analog circuits","authors":"J. Savir, Zhen Guo","doi":"10.1109/ATS.2002.1181682","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181682","url":null,"abstract":"This paper investigates the detectability of parameter faults in linear, time-invariant, analog circuits. We show that there are inherent limitations with regard to analog faults detectability.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128680340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181737
Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Y. Lin
The test scheduling of memory cores can significantly affect the test time and power of system chips. We propose a test scheduling algorithm for BISTed memory cores to minimize the overall testing time under the test power constraint. The proposed algorithm combines several approaches for a near-optimal result, based on the properties of BISTed memory cores. By proper partitioning, an analytic exhaustive search finds optimal results for large memory cores, while a heuristic ordering with simulated annealing further handles a large amount of smaller memory cores. On the average, the results are within 1% difference of the optimal solution for the cases of 200 memory cores.
{"title":"Test scheduling of BISTed memory cores for SoC","authors":"Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Y. Lin","doi":"10.1109/ATS.2002.1181737","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181737","url":null,"abstract":"The test scheduling of memory cores can significantly affect the test time and power of system chips. We propose a test scheduling algorithm for BISTed memory cores to minimize the overall testing time under the test power constraint. The proposed algorithm combines several approaches for a near-optimal result, based on the properties of BISTed memory cores. By proper partitioning, an analytic exhaustive search finds optimal results for large memory cores, while a heuristic ordering with simulated annealing further handles a large amount of smaller memory cores. On the average, the results are within 1% difference of the optimal solution for the cases of 200 memory cores.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123340032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181693
A. Benso, S. Carlo, G. D. Natale, P. Prinetto
This paper presents a new fault simulator architecture for RAM memories. The key features of the proposed tool are: (1) user-definable fault models, test algorithm, and memory architecture; (2) very fast simulation algorithm; (3) ability to compute the coverage of any provided test sequence with respect to a user-defined set of fault models, and to eliminate redundant operations; (4) assessment of the power consumption generated by the test application. Moreover, the tool is able to modify the test algorithm in order to guarantee the compliance to user-defined power consumption constraints.
{"title":"Specification and design of a new memory fault simulator","authors":"A. Benso, S. Carlo, G. D. Natale, P. Prinetto","doi":"10.1109/ATS.2002.1181693","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181693","url":null,"abstract":"This paper presents a new fault simulator architecture for RAM memories. The key features of the proposed tool are: (1) user-definable fault models, test algorithm, and memory architecture; (2) very fast simulation algorithm; (3) ability to compute the coverage of any provided test sequence with respect to a user-defined set of fault models, and to eliminate redundant operations; (4) assessment of the power consumption generated by the test application. Moreover, the tool is able to modify the test algorithm in order to guarantee the compliance to user-defined power consumption constraints.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121711391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181722
Sheng-Hung Hsieh, Ming-Jun Hsiao, Tsin-Yuan Chang
In this paper. an embedded built-in-self-test approach for analog-to-digital converters (ADCs) is presented. This architecture can test the parameters of ADC. which includes the differential nonlinearity (DNL) error, integral nonlinearity (INL) error, offset error (V/sub OSE/), gain error (V/sub GE/), and sampling rate. The proposed circuit is designed and simulated with an 8-bit ADC by using a CMOS 0.35 /spl mu/m 1P4M process. The accuracy of DNL test, INL test, VOSE test, and VGE test depend on the testing time. For the case of 256/spl mu/s, the accuracy can achieve 1/10LSB. and longer testing time results in higher accuracy.
{"title":"An embedded built-in-self-test approach for analog-to-digital converters","authors":"Sheng-Hung Hsieh, Ming-Jun Hsiao, Tsin-Yuan Chang","doi":"10.1109/ATS.2002.1181722","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181722","url":null,"abstract":"In this paper. an embedded built-in-self-test approach for analog-to-digital converters (ADCs) is presented. This architecture can test the parameters of ADC. which includes the differential nonlinearity (DNL) error, integral nonlinearity (INL) error, offset error (V/sub OSE/), gain error (V/sub GE/), and sampling rate. The proposed circuit is designed and simulated with an 8-bit ADC by using a CMOS 0.35 /spl mu/m 1P4M process. The accuracy of DNL test, INL test, VOSE test, and VGE test depend on the testing time. For the case of 256/spl mu/s, the accuracy can achieve 1/10LSB. and longer testing time results in higher accuracy.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124378926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181741
Harald J. Zainzinger
In this paper the author presents a generic test equipment for embedded platform software. This approach helps to overcome the paradigms of modern software development like object-oriented concepts, rapid prototyping and communication-support over a large number of different protocols. As different platforms are supported, the most relevant differences between compilers, processors and operating systems are described. Since testers of embedded systems are usually familiar with C and C++, the test equipment is based on CINT, a C++ interpreter. The last section of this paper investigates the advantages and drawbacks of CINT.
{"title":"Testing embedded systems by using a C++ script interpreter","authors":"Harald J. Zainzinger","doi":"10.1109/ATS.2002.1181741","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181741","url":null,"abstract":"In this paper the author presents a generic test equipment for embedded platform software. This approach helps to overcome the paradigms of modern software development like object-oriented concepts, rapid prototyping and communication-support over a large number of different protocols. As different platforms are supported, the most relevant differences between compilers, processors and operating systems are described. Since testers of embedded systems are usually familiar with C and C++, the test equipment is based on CINT, a C++ interpreter. The last section of this paper investigates the advantages and drawbacks of CINT.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124072069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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