An Inductorless 5-GHz Differential Dual Regulated Cross-Cascode Transimpedance Amplifier using 40 nm CMOS

Abstract

This paper presents a new inductorless 5-GHz differential dual regulated cross-cascode transimpedance amplifier (DDRCCTIA) using UMC 40 nm CMOS technology. It consists of a differential cross-coupled input stage (DDRCC) that has a unique dual PMOS and NMOS regulated cascode loops as well as a frequency doubler with active inductor (FDAI) buffer stage. The design has a transimpedance gain of 62.5 dBΩ and bandwidth of 5.02 GHz. The power consumption is 7.34 mW from a 1.8 V supply, input referred noise current of 4.5 pA√Hz and a very small core area of 0.0018 mm2.