An InP HBT low power receiver IC integrating AGC amplifier, clock recovery circuit and demultiplexers

Abstract

The authors designed and fabricated a highly integrated and very low power receiver IC for 2.5 Gb/s optical communication. It consisted of an AGC data recovery circuit and demultiplexer, and consumed only 340 mW power. The measured data have validated our design approach and have demonstrated the potential of the InP HBT technology to integrate analog and digital functions for low power and high speed applications. Achieving even lower power is feasible through device scaling. Additional functionality such as multiple data rate, frequency detection, lock indicator and data decoder can be included in future integration.