A Low-Power 40 Gbit/s Receiver Circuit Based on Full-Swing CMOS-Style Clocking

Abstract

We describe circuit techniques for a 40 Gbit/s CMOS CDR circuit in 65 nm CMOS-SOI technology, which mostly uses a full-swing CMOS circuit style to minimize power and area. The quarter rate receiver uses a phase-programmable PLL (P-PLL) architecture for clock generation and phase tracking, and implements a high-speed sampler based on CMOS SenseAmp latches. The circuit uses 0.03mm2 of chip area, and consumes 72m\V of power at 40 Gbps data rate. We describe in detail the implementation of several crucial components, i.e. the ring VCO, which was optimized for high-speed operation, and the sampling and demultiplexing stage.