Analysis techniques for real-time, fault-tolerant, VLSI processing arrays

Abstract

Several techniques are described for the quantitative evaluation of the effectiveness of various reconfiguration strategies for real-time, VLSI processing arrays. The first technique illustrates the advantages of small, easily managed semi-Markov models for comparing important events in the fault/error process of a system. Since these events have the greatest impact on architecture selection in a real-time system, a methodology that quantifies system differences is necessary to properly design a real-time processing array. The second technique developed for this research expands the previous concept to include the events within a single time interval in a real-time system. The single interval model provides unique information on critical real-time design issues. It quantitatively describes the effects of time-outs on the failure probability of potential reconfiguration strategies. The interaction of sampling rate and failures due to time-outs is clarified with this model. The ability to recover from faults at different points within an interval is also estimated.