Clock generation and distribution for the third generation Itanium/spl reg/ processor

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221148

S. Tam, U. Desai, R. Limaye

引用次数: 13

Abstract

The clock generation and distribution system for the third generation Itanium/spl reg/ processor operates at 1.5 GHz with a skew of 24 ps. Clock optimization fuses enable post-silicon speed path balancing for higher performance.

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第三代Itanium/spl reg/处理器的时钟生成和分布

第三代Itanium/spl reg/处理器的时钟生成和分配系统工作在1.5 GHz，倾斜为24 ps。时钟优化保险丝使后硅速度路径平衡具有更高的性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

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