A diagnostic model for detecting functional violation in HDL-code of System-on-Chip

Abstract

The design of System-on-Chip (SoC) is becoming more difficult by the day with the increase in complexity of consumer requirements and time-to-market pressures. The use of HDLs in the design of digital system has become more ubiquitous and challenging as ever if timely delivery of product with increased yield is to be achieved. A technological and process-efficient models and methods for diagnosis of functional violations in software and/ or hardware products are proposed. The assertion-based transaction graph used in this model can be transformed into a tabular data structure that focuses on parallel execution of logic operations when searching for defective components or blocks with functional violation in HDL models.