ML-Based Wire RC Prediction in Monolithic 3D ICs with an Application to Full-Chip Optimization

S. Pentapati, B. W. Ku, S. Lim
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引用次数: 3

Abstract

The state-of-the-art Monolithic 3D (M3D) IC design methodologies~\citem3d:Ku-tcad-Compact2D, m3d:Panth-tcad-Shrunk2D use commercial electronic design automation tools built for 2D ICs to implement a pseudo-3D design and split it into two dies that are routed independently to create an M3D design. Therefore, an accurate estimation of 3D wire parasitics at the pseudo-3D stage is important to achieve a well optimized M3D design. In this paper, we present a regression model based on boosted decision tree learning to better predict the 3D wire parasitics (RCs) at the pseudo-3D stage. Our model is trained using individual net features as well as the full-chip design metrics using multiple instantiations of 8 different netlists and is tested on 3 unseen netlists. Compared to the Compact-2D~\citem3d:Ku-tcad-Compact2D flow on its own as the reference pseudo-3D, the addition of our predictive model achieves up to $2.9 \times$ and $1.7 \times$ smaller root mean square error in the resistance and capacitance predictions respectively. On an unseen netlist design, we observe that our model provides 98.6% and 94.6% RC prediction accuracy in 3D and up to $6.4 \times$ smaller total negative slack of the design compared to the result of Compact-2D flow resulting in a more timing-robust M3D IC. This model is not limited to Compact-2D, and can be extended to other pseudo-3D flows.
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基于ml的单片三维集成电路导线RC预测及其在全芯片优化中的应用
最先进的单片3D (M3D) IC设计方法~\citem3d:Ku-tcad-Compact2D, M3D: panth -tcad- smallk2d使用为2D IC构建的商业电子设计自动化工具来实现伪3D设计,并将其拆分为两个独立路由的芯片以创建M3D设计。因此,在拟三维阶段准确估计三维导线寄生对实现优化的M3D设计至关重要。本文提出了一种基于增强决策树学习的回归模型,以更好地预测伪三维阶段的三维导线寄生(rc)。我们的模型使用单个网络特征以及使用8个不同网络列表的多个实例的全芯片设计指标进行训练,并在3个未见过的网络列表上进行测试。与Compact-2D~\citem3d:Ku-tcad-Compact2D流本身作为参考伪3d相比,我们的预测模型在电阻和电容预测中分别实现了2.9倍和1.7倍的均方根误差。在一个未见过的网表设计中,我们观察到我们的模型在3D中提供了98.6%和94.6%的RC预测精度,并且与Compact-2D流的结果相比,设计的总负松弛量减少了6.4倍,从而产生了更具时序鲁棒性的M3D IC。该模型不仅限于Compact-2D,而且可以扩展到其他伪3D流。
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Reinforcement Learning for Placement Optimization Session details: Session 8: Monolithic 3D and Packaging Session ISPD 2021 Wafer-Scale Physics Modeling Contest: A New Frontier for Partitioning, Placement and Routing Scalable System and Silicon Architectures to Handle the Workloads of the Post-Moore Era A Lifetime of ICs, and Cross-field Exploration: ISPD 2021 Lifetime Achievement Award Bio
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